> Wiadomość napisana przez Peter Geis <pgwipeout@xxxxxxxxx> w dniu 26.01.2022, o godz. 21:24:
>
> The hdmi-cec clock must be 32khz in order for cec to work correctly.
> Ensure after enabling the clock we set it in order for the hardware to
> work as expected.
> Warn on failure, in case this is a static clock that is slighty off.
> Fixes hdmi-cec support on Rockchip devices.
>
> Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
>
> Signed-off-by: Peter Geis <pgwipeout@xxxxxxxxx>
> ---
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> index 54d8fdad395f..1a96da60e357 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> @@ -48,6 +48,9 @@
>
> #define HDMI14_MAX_TMDSCLK 340000000
>
> +/* HDMI CEC needs a clock rate of 32khz */
> +#define HDMI_CEC_CLK_RATE 32768
> +
> enum hdmi_datamap {
> RGB444_8B = 0x01,
> RGB444_10B = 0x03,
> @@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
> ret);
> goto err_iahb;
> }
> +
> + ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
> + if (ret)
> + dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);
> }
>
> /* Product and revision IDs */
> --
> 2.25.1
>
>
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Peter,
On my 5.17-rc7 with applied rk356x VOP2 v8 series - this patch makes CEC working on rk3566.
Unfortunately it breaks working ok CEC on rk3399 rockpi-4b.
Reverting this patch brings back CEC on rk3399 - but rk3366 becomes with non working CEC
I'm not sure how to move forward with this....
br
