The hdmi-cec clock must be 32khz in order for cec to work correctly.
Ensure after enabling the clock we set it in order for the hardware to
work as expected.
Warn on failure, in case this is a static clock that is slighty off.
Fixes hdmi-cec support on Rockchip devices.
Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
Signed-off-by: Peter Geis <pgwipeout@xxxxxxxxx>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 54d8fdad395f..1a96da60e357 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -48,6 +48,9 @@
#define HDMI14_MAX_TMDSCLK 340000000
+/* HDMI CEC needs a clock rate of 32khz */
+#define HDMI_CEC_CLK_RATE 32768
+
enum hdmi_datamap {
RGB444_8B = 0x01,
RGB444_10B = 0x03,
@@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
ret);
goto err_iahb;
}
+
+ ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
+ if (ret)
+ dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);
}
/* Product and revision IDs */
--
2.25.1
