On Fri, Mar 4, 2022 at 5:55 AM Marek Vasut <marex@xxxxxxx> wrote: > > The chip contains fractional PLL, however the driver currently hard-codes > one specific PLL setting. Implement generic PLL parameter calculation code, > so any DPI panel with arbitrary pixel clock can be attached to this bridge. > > The datasheet for this bridge is not available, the PLL behavior has been > inferred from [1] and [2] and by analyzing the DPI pixel clock with scope. > The PLL limits might be wrong, but at least the calculated values match all > the example code available. This is better than one hard-coded pixel clock > value anyway. > > [1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/gpu/drm/bridge/icn6211.c > [2] https://github.com/tdjastrzebski/ICN6211-Configurator > > Acked-by: Maxime Ripard <maxime@xxxxxxxxxx> > Signed-off-by: Marek Vasut <marex@xxxxxxx> > Cc: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx> > Cc: Maxime Ripard <maxime@xxxxxxxxxx> > Cc: Robert Foss <robert.foss@xxxxxxxxxx> > Cc: Sam Ravnborg <sam@xxxxxxxxxxxx> > Cc: Thomas Zimmermann <tzimmermann@xxxxxxx> > To: dri-devel@xxxxxxxxxxxxxxxxxxxxx > --- > V2: Rebase on next-20220214 > V3: Add AB from Maxime > --- > drivers/gpu/drm/bridge/chipone-icn6211.c | 87 +++++++++++++++++++++++- > 1 file changed, 84 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c b/drivers/gpu/drm/bridge/chipone-icn6211.c > index df8e75a068ad0..71c83a18984fa 100644 > --- a/drivers/gpu/drm/bridge/chipone-icn6211.c > +++ b/drivers/gpu/drm/bridge/chipone-icn6211.c > @@ -163,6 +163,87 @@ static inline int chipone_dsi_write(struct chipone *icn, const void *seq, > chipone_dsi_write(icn, d, ARRAY_SIZE(d)); \ > } > > +static void chipone_configure_pll(struct chipone *icn, > + const struct drm_display_mode *mode) > +{ > + unsigned int best_p = 0, best_m = 0, best_s = 0; > + unsigned int delta, min_delta = 0xffffffff; > + unsigned int freq_p, freq_s, freq_out; > + unsigned int p_min, p_max; > + unsigned int p, m, s; > + unsigned int fin; > + > + /* > + * DSI clock lane frequency (input into PLL) is calculated as: > + * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2 > + * the 2 is there because the bus is DDR. > + * > + * DPI pixel clock frequency (output from PLL) is mode clock. > + * > + * The chip contains fractional PLL which works as follows: > + * DPI_CLK = ((DSI_CLK / P) * M) / S > + * P is pre-divider, register PLL_REF_DIV[3:0] is 2^(n+1) divider > + * register PLL_REF_DIV[4] is extra 1:2 divider > + * M is integer multiplier, register PLL_INT(0) is multiplier > + * S is post-divider, register PLL_REF_DIV[7:5] is 2^(n+1) divider > + * > + * It seems the PLL input clock after applying P pre-divider have > + * to be lower than 20 MHz. > + */ > + fin = mode->clock * mipi_dsi_pixel_format_to_bpp(icn->dsi->format) / no dsi in chipone structure. please preserve format during the probe. drivers/gpu/drm/bridge/chipone-icn6211.c:193:61: error: ‘struct chipone’ has no member named ‘dsi’ 193 | fin = mode->clock * mipi_dsi_pixel_format_to_bpp(icn->dsi->format) / Thanks, Jagan.
