We have to specify in the Render Control Unit Mode register
when CCS is enabled.
v2:
- Move RCU_MODE programming to a helper function. (Tvrtko)
- Clean up and clarify comments. (Tvrtko)
- Add RCU_MODE to the GuC save/restore list. (Daniele)
Bspec: 46034
Original-author: Michel Thierry
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx>
Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxxxxxxx>
Cc: Vinay Belgaumkar <vinay.belgaumkar@xxxxxxxxx>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@xxxxxxxxx>
Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 2 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17 +++++++++++++++++
.../drm/i915/gt/intel_execlists_submission.c | 16 ++++++++++++++++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 16 ++++++++++++++++
4 files changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index be4b1e65442f..1c0ab05c3c40 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -265,6 +265,8 @@ intel_engine_create_pinned_context(struct intel_engine_cs *engine,
void intel_engine_destroy_pinned_context(struct intel_context *ce);
+void xehp_enable_ccs_engines(struct intel_engine_cs *engine);
+
#define ENGINE_PHYSICAL 0
#define ENGINE_MOCK 1
#define ENGINE_VIRTUAL 2
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 2136c56d3abc..92f4cf9833ee 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -2070,6 +2070,23 @@ intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine)
return active;
}
+void xehp_enable_ccs_engines(struct intel_engine_cs *engine)
+{
+ /*
+ * If there are any non-fused-off CCS engines, we need to enable CCS
+ * support in the RCU_MODE register. This only needs to be done once,
+ * so for simplicity we'll take care of this in the RCS engine's
+ * resume handler; since the RCS and all CCS engines belong to the
+ * same reset domain and are reset together, this will also take care
+ * of re-applying the setting after i915-triggered resets.
+ */
+ if (!CCS_MASK(engine->gt))
+ return;
+
+ intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
+ _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "mock_engine.c"
#include "selftest_engine.c"
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index c8407cc96c42..574c0542c92f 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2914,6 +2914,19 @@ static int execlists_resume(struct intel_engine_cs *engine)
return 0;
}
+static int gen12_rcs_resume(struct intel_engine_cs *engine)
+{
+ int ret;
+
+ ret = execlists_resume(engine);
+ if (ret)
+ return ret;
+
+ xehp_enable_ccs_engines(engine);
+
+ return 0;
+}
+
static void execlists_reset_prepare(struct intel_engine_cs *engine)
{
ENGINE_TRACE(engine, "depth<-%d\n",
@@ -3468,6 +3481,9 @@ static void rcs_submission_override(struct intel_engine_cs *engine)
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
break;
}
+
+ if (engine->class == RENDER_CLASS)
+ engine->resume = gen12_rcs_resume;
}
int intel_execlists_submission_setup(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 6db8bb1982ca..7e42fecd6093 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3619,6 +3619,19 @@ static bool guc_sched_engine_disabled(struct i915_sched_engine *sched_engine)
return !sched_engine->tasklet.callback;
}
+static int gen12_rcs_resume(struct intel_engine_cs *engine)
+{
+ int ret;
+
+ ret = guc_resume(engine);
+ if (ret)
+ return ret;
+
+ xehp_enable_ccs_engines(engine);
+
+ return 0;
+}
+
static void guc_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = guc_submit_request;
@@ -3739,6 +3752,9 @@ static void rcs_submission_override(struct intel_engine_cs *engine)
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
break;
}
+
+ if (engine->class == RENDER_CLASS)
+ engine->resume = gen12_rcs_resume;
}
static inline void guc_default_irqs(struct intel_engine_cs *engine)
--
2.34.1
