Quoting Kuogee Hsieh (2022-02-22 16:27:39) > Widebus feature will transmit two pixel data per pixel clock to interface. > Timing engine provides driving force for this purpose. This patch base > on HPG (Hardware Programming Guide) to revise timing engine register > setting to accommodate both widebus and non widebus application. Also > horizontal width parameters need to be reduced by half since two pixel > data are clocked out per pixel clock when widebus feature enabled. > > Widebus can be enabled individually at DP. However at DSI, widebus have > to be enabled along with DSC to achieve pixel clock rate be scaled down > with same ratio as compression ratio when 10 bits per source component. > Therefore this patch add no supports of DSI related widebus and compression. > > Changes in v2: > -- remove compression related code from timing > -- remove op_info from struct msm_drm_private > -- remove unnecessary wide_bus_en variables > -- pass wide_bus_en into timing configuration by struct msm_dp > > Changes in v3: > -- split patch into 3 patches > > Changes in v4: > -- rework timing engine to not interfere with dsi/hdmi > -- cover both widebus and compression > > Changes in v5: > -- remove supports of DSI widebus and compression > > Changes in v7: > -- split this patch into 3 patches > -- add Tested-by > > Changes in v8: > -- move new registers writes under DATA_HCTL_EN features check. > > Changes in v10: > -- add const inside dpu_encoder_is_widebus_enabled() > -- drop useless parenthesis please > > Signed-off-by: Kuogee Hsieh <quic_khsieh@xxxxxxxxxxx> > Tested-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> > --- Reviewed-by: Stephen Boyd <swboyd@xxxxxxxxxxxx>
