Re: [PATCH v8 3/4] drm/msm/dpu: revise timing engine programming to support widebus feature

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On 2/18/2022 6:53 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-02-17 13:36:27)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 0d315b4..0c22839 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -217,6 +219,14 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
         15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
  };

+
+bool dpu_encoder_is_widebus_enabled(struct drm_encoder *drm_enc)
const?

+{
+       struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
const?

+
+       return dpu_enc->wide_bus_en;
+}
+
  static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
  {
         struct dpu_hw_dither_cfg dither_cfg = { 0 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 99a5d73..893d74d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -168,4 +168,6 @@ int dpu_encoder_get_linecount(struct drm_encoder *drm_enc);
   */
  int dpu_encoder_get_frame_count(struct drm_encoder *drm_enc);

+bool dpu_encoder_is_widebus_enabled(struct drm_encoder *drm_enc);
const drm_enc?

+
  #endif /* __DPU_ENCODER_H__ */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index c2cd185..4e4fa56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -147,17 +156,36 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
         hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
         display_hctl = (hsync_end_x << 16) | hsync_start_x;

-       if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) {
+       /*
+        * DATA_HCTL_EN controls data timing which can be different from
+        * video timing. It is recommended to enable it for all cases, except
+        * if compression is enabled in 1 pixel per clock mode
+        */
+       if (p->wide_bus_en)
+               intf_cfg2 |= (INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN);
Drop useless parenthesis please.

+
+       data_width = p->width;
+
+       hsync_data_start_x = hsync_start_x;
+       hsync_data_end_x =  hsync_start_x + data_width - 1;
+
+       display_data_hctl = (hsync_data_end_x << 16) | hsync_data_start_x;
+
+       if (dp_intf) {
+               /* DP timing adjustment */
+               display_v_start += p->hsync_pulse_width + p->h_back_porch;
+               display_v_end   -= p->h_front_porch;
Is this code movement intentional?
yes, this timing adjustment is required for DP/eDP

+
                 active_h_start = hsync_start_x;
                 active_h_end = active_h_start + p->xres - 1;
                 active_v_start = display_v_start;
display_v_start is different now.

                 active_v_end = active_v_start + (p->yres * hsync_period) - 1;

-               display_v_start += p->hsync_pulse_width + p->h_back_porch;
-               display_v_end   -= p->h_front_porch;
-
                 active_hctl = (active_h_end << 16) | active_h_start;
                 display_hctl = active_hctl;
+
+               intf_cfg |= INTF_CFG_ACTIVE_H_EN;
+               intf_cfg |= INTF_CFG_ACTIVE_V_EN;
		  intf_cfg |= INTF_CFG_ACTIVE_H_EN | INTF_CFG_ACTIVE_V_EN;

would be one less line.



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