On Thu, Feb 10, 2022 at 10:36:31AM -0800, Michael Cheng wrote:
> Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
> performs a flush by first performing a clean, follow by an invalidation
> operation.
>
> v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
> dcache.
>
> v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h
>
> v4 (Michael Cheng): Rebase
>
> v5 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
Note that you only really need to indicate that you're the one making
these updates in cases where you're picking up someone else's patch and
carrying it forward; otherwise it's pretty clear that you were also the
author of v2-v5.
However when possible it is a good idea to indicate who suggested
various changes you're making. E.g., I think a lot of these were based
on feedback from Tvrtko?
>
> Signed-off-by: Michael Cheng <michael.cheng@xxxxxxxxx>
Change appears to accurately implement the same type of cache flush as
what we have on the x86 backend.
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/drm_cache.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> index 66597e411764..2e233f53331e 100644
> --- a/drivers/gpu/drm/drm_cache.c
> +++ b/drivers/gpu/drm/drm_cache.c
> @@ -28,6 +28,7 @@
> * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
> */
>
> +#include <linux/cacheflush.h>
> #include <linux/cc_platform.h>
> #include <linux/export.h>
> #include <linux/highmem.h>
> @@ -174,6 +175,11 @@ drm_clflush_virt_range(void *addr, unsigned long length)
>
> if (wbinvd_on_all_cpus())
> pr_err("Timed out waiting for cache flush\n");
> +
> +#elif defined(CONFIG_ARM64)
> + void *end = addr + length;
> + dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
> +
> #else
> WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
> #endif
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
