On Fri, 18 Feb 2022 at 00:36, Kuogee Hsieh <quic_khsieh@xxxxxxxxxxx> wrote:
>
> To improve code readability, this patch replace BIT(x) with
> correspond register bit define string
>
> Signed-off-by: Kuogee Hsieh <quic_khsieh@xxxxxxxxxxx>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index 284f561..c2cd185 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -60,6 +60,12 @@
>
> #define INTF_MUX 0x25C
>
> +#define INTF_CFG_ACTIVE_H_EN BIT(29)
> +#define INTF_CFG_ACTIVE_V_EN BIT(30)
> +
> +#define INTF_CFG2_DATABUS_WIDEN BIT(0)
> +#define INTF_CFG2_DATA_HCTL_EN BIT(4)
> +
> static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
> const struct dpu_mdss_cfg *m,
> void __iomem *addr,
> @@ -130,13 +136,13 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
>
> if (active_h_end) {
> active_hctl = (active_h_end << 16) | active_h_start;
> - intf_cfg |= BIT(29); /* ACTIVE_H_ENABLE */
> + intf_cfg |= INTF_CFG_ACTIVE_H_EN;
> } else {
> active_hctl = 0;
> }
>
> if (active_v_end)
> - intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */
> + intf_cfg |= INTF_CFG_ACTIVE_V_EN;
>
> hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
> display_hctl = (hsync_end_x << 16) | hsync_start_x;
> @@ -182,7 +188,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
> (0x21 << 8));
>
> if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) {
> - intf_cfg2 |= BIT(4);
> + intf_cfg2 |= INTF_CFG2_DATA_HCTL_EN;
> display_data_hctl = display_hctl;
> DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);
> DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl);
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
With best wishes
Dmitry
