This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.
v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
more patches to convert additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)
v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
v4: Remove extra memory barriers
v5: s/cache_clflush_range/drm_clflush_virt_range
v6: Fix up "Drop invalidate_csb_entries" to use correct parameters. Also
added in arm64 support for drm_clflush_virt_range.
v7: Re-order patches, and use correct macro for dcache flush for arm64.
v8: Remove ifdef for asm/cacheflush.
Michael Cheng (6):
drm: Add arch arm64 for drm_clflush_virt_range
drm/i915/gt: Re-work intel_write_status_page
drm/i915/gt: Drop invalidate_csb_entries
drm/i915/gt: Re-work reset_csb
drm/i915/: Re-work clflush_write32
drm/i915/gt: replace cache_clflush_range
drivers/gpu/drm/drm_cache.c | 5 +++++
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++++++------
drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
.../drm/i915/gt/intel_execlists_submission.c | 19 ++++++-------------
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
8 files changed, 27 insertions(+), 36 deletions(-)
--
2.25.1
