On 24-01-22, 10:40, Liu Ying wrote: > The D-PHY specification (v1.2) explicitly mentions that the T-CLK-PRE > parameter's unit is Unit Interval(UI) and the minimum value is 8. Also, > kernel doc of the 'clk_pre' member of struct phy_configure_opts_mipi_dphy > mentions that it should be in UI. However, the dphy core driver wrongly > sets 'clk_pre' to 8000, which seems to hint that it's in picoseconds. > > So, let's fix the dphy core driver to correctly reflect the T-CLK-PRE > parameter's minimum value according to the D-PHY specification. > > I'm assuming that all impacted custom drivers shall program values in > TxByteClkHS cycles into hardware for the T-CLK-PRE parameter. The D-PHY > specification mentions that the frequency of TxByteClkHS is exactly 1/8 > the High-Speed(HS) bit rate(each HS bit consumes one UI). So, relevant > custom driver code is changed to program those values as > DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE), then. > > Note that I've only tested the patch with RM67191 DSI panel on i.MX8mq EVK. > Help is needed to test with other i.MX8mq, Meson and Rockchip platforms, > as I don't have the hardwares. Applied, thanks -- ~Vinod
