The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI glue on the same Amlogic SoCs. This adds support for the glue managing the transceiver, mimicing the init flow provided by Amlogic to setup the ENCL encoder, the glue, the transceiver, the digital D-PHY and the Analog PHY in the proper way. The DW-MIPI-DSI transceiver + D-PHY are clocked by the GP0 PLL, and the ENCL encoder + VIU pixel reader by the VCLK2 clock using the HDMI PLL. The DW-MIPI-DSI transceiver gets this pixel stream as input clocked with the VCLK2 clock. An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the DW-MIPI-DSI transceiver. This patchset is based on an earlier attempt at [1] for the AXG SoCs, but: - the AXG has a single clock source for both transceiver + pixel, which makes it an exception instead of a rule, it's simpler to add support for G12A then add AXG on it - previous glue code was a single monolitic code mixing encoders & bridges, this version is aligned on the previous cleanup done on HDMI & CVBS bridges architecture at [2] - since the only output of AXG is DSI, AXG VPU support is post-poned until we implement single-clock DSI support specific case on top of this. Changes from v1 at [3]: - fixed DSI host bindings - add reviewed-by tags for bindings - moved magic values to defines thanks to Martin's searches - added proper prefixes to defines - moved phy_configure to phy_init() dw-mipi-dsi callback - moved phy_on to a new phy_power_on() dw-mipi-dsi callback - correctly return phy_init/configure errors to callback returns [1] https://lore.kernel.org/r/20200907081825.1654-1-narmstrong@xxxxxxxxxxxx [2] https://lore.kernel.org/r/20211020123947.2585572-1-narmstrong@xxxxxxxxxxxx Neil Armstrong (6): dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings dt-bindings: display: meson-vpu: add third DPI output port drm/meson: venc: add ENCL encoder setup for MIPI-DSI output drm/meson: vclk: add DSI clock config drm/meson: add DSI encoder drm/meson: add support for MIPI-DSI transceiver .../display/amlogic,meson-dw-mipi-dsi.yaml | 116 ++++++ .../bindings/display/amlogic,meson-vpu.yaml | 5 + drivers/gpu/drm/meson/Kconfig | 7 + drivers/gpu/drm/meson/Makefile | 3 +- drivers/gpu/drm/meson/meson_drv.c | 7 + drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 357 ++++++++++++++++++ drivers/gpu/drm/meson/meson_dw_mipi_dsi.h | 160 ++++++++ drivers/gpu/drm/meson/meson_encoder_dsi.c | 160 ++++++++ drivers/gpu/drm/meson/meson_encoder_dsi.h | 12 + drivers/gpu/drm/meson/meson_registers.h | 15 + drivers/gpu/drm/meson/meson_vclk.c | 47 +++ drivers/gpu/drm/meson/meson_vclk.h | 1 + drivers/gpu/drm/meson/meson_venc.c | 211 ++++++++++- drivers/gpu/drm/meson/meson_venc.h | 6 + drivers/gpu/drm/meson/meson_vpp.h | 2 + 15 files changed, 1106 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.h create mode 100644 drivers/gpu/drm/meson/meson_encoder_dsi.c create mode 100644 drivers/gpu/drm/meson/meson_encoder_dsi.h -- 2.25.1
