Hi Dmitry, On Wed, Jan 12, 2022 at 04:28:41PM +0300, Dmitry Osipenko wrote: > 14.09.2021 12:35, Maxime Ripard пишет: > > Hi, > > > > This is a follow-up of the discussion here: > > https://lore.kernel.org/linux-clk/20210319150355.xzw7ikwdaga2dwhv@gilmour/ > > > > This implements a mechanism to raise and lower clock rates based on consumer > > workloads, with an example of such an implementation for the RaspberryPi4 HDMI > > controller. > > > > There's a couple of things worth discussing: > > > > - The name is in conflict with clk_request_rate, and even though it feels > > like the right name to me, we should probably avoid any confusion > > > > - The code so far implements a policy of always going for the lowest rate > > possible. While we don't have an use-case for something else, this should > > maybe be made more flexible? > > Hello Maxime, > > On NVIDIA Tegra we use interconnect framework for converting of > workload-based memory bandwidth requirement to the memory clock rate > [1]. All Tegra SoCs have two display controllers and other memory > clients, ICC takes care of summing and updating memory bandwidth for us, > which in the end results in a freq change of the shared memory controller. > > [1] https://git.kernel.org/linus/04d5d5df9 > > Not so long time ago me and Thierry Reding were looking at yours v1 and > back then Thierry suggested that the same ICC approach might work for > yours case. I'm now looking at the v2 and yours discussion with Stephen > Boyd, and it appears that ICC is indeed what you really need. Have you > considered to use ICC? The goals seem to be similar indeed, but most of these clocks feed some internal state machine in those devices and are not related to the memory bandwidth at all. So there's no real interconnect to model there :/ Maxime
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