On Mon, Jan 10, 2022 at 05:06:03PM +0300, Dmitry Baryshkov wrote: > On Mon, 10 Jan 2022 at 15:56, Rajeev Nandan <quic_rajeevny@xxxxxxxxxxx> wrote: > > > > In most cases, the default values of DSI PHY tuning registers should be > > sufficient as they are fully optimized. However, in some cases where > > extreme board parasitics cause the eye shape to degrade, the override > > bits can be used to improve the signal quality. > > > > The general guidelines for DSI PHY tuning include: > > - High and moderate data rates may benefit from the drive strength and > > drive level tuning. > > - Drive strength tuning will affect the output impedance and may be used > > for matching optimization. > > - Drive level tuning will affect the output levels without affecting the > > impedance. > > > > The clock and data lanes have a calibration circuitry feature. The drive > > strength tuning can be done by adjusting rescode offset for hstop/hsbot, > > and the drive level tuning can be done by adjusting the LDO output level > > for the HSTX drive. > > > > Signed-off-by: Rajeev Nandan <quic_rajeevny@xxxxxxxxxxx> > > --- > > > > Changes in v2: > > - More details in the commit text (Stephen Boyd) > > - Use human understandable values (Stephen Boyd, Dmitry Baryshkov) > > - Do not take values that are going to be unused (Dmitry Baryshkov) > > > > .../bindings/display/msm/dsi-phy-10nm.yaml | 33 ++++++++++++++++++++++ > > 1 file changed, 33 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml > > index 4399715..d0eb8f6 100644 > > --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml > > +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml > > @@ -35,6 +35,35 @@ properties: > > Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and > > connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target > > Generic note: > I think these properties should be prefixed with "qcom," prefix. > > > > > + phy-rescode-offset-top: > > + $ref: /schemas/types.yaml#/definitions/uint8-array > > + minItems: 5 > > + maxItems: 5 > > + description: > > + Integer array of offset for pull-up legs rescode for all five lanes. > > + To offset the drive strength from the calibrated value in an increasing > > + or decreasing manner, use 6 bit two’s complement values. > > dtc should support negative values, google hints that <(-2)> should work. Yes, but the schema checks don't check negative values correctly yet. So you can use 'int8-array', but just don't use negative values in the examples. I'm working on changes that will fix this issue. What does 6-bit mean? 0x3f is negative? Just sign extend the values and specify the valid range instead: minimum: -32 maximum: 31 Rob
