On 12/18/21 10:50 PM, Antonio Borneo wrote:
The dsi has several constraints on the video modes it can support, mainly due to the frequencies that can be generated by the PLL integrated in the DSI device. Verify that the required HS clock can be generated by the PLL. The dsi clock from the dsi PLL and the ltdc pixel clock are asynchronous. The dsi needs to return in LP mode during HFP or HBP to re-synchronize at each video line. Verify that the duration of HFP and HBP allows the dsi to enter in LP mode. Signed-off-by: Antonio Borneo <antonio.borneo@xxxxxxxxxxx> --- To: David Airlie <airlied@xxxxxxxx> To: Daniel Vetter <daniel@xxxxxxxx> To: Andrzej Hajda <a.hajda@xxxxxxxxxxx> To: Neil Armstrong <narmstrong@xxxxxxxxxxxx> To: Robert Foss <robert.foss@xxxxxxxxxx> To: Laurent Pinchart <Laurent.pinchart@xxxxxxxxxxxxxxxx> To: Jonas Karlman <jonas@xxxxxxxxx> To: Jernej Skrabec <jernej.skrabec@xxxxxxxxx> To: Yannick Fertre <yannick.fertre@xxxxxxxxxxx> To: Philippe Cornu <philippe.cornu@xxxxxxxxxxx> To: Benjamin Gaignard <benjamin.gaignard@xxxxxxxxxx> To: Maxime Coquelin <mcoquelin.stm32@xxxxxxxxx> To: Alexandre Torgue <alexandre.torgue@xxxxxxxxxxx> To: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx> To: dri-devel@xxxxxxxxxxxxxxxxxxxxx To: linux-stm32@xxxxxxxxxxxxxxxxxxxxxxxxxxxx To: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx Cc: linux-kernel@xxxxxxxxxxxxxxx --- drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 98 +++++++++++++++++++++++++++ 1 file changed, 98 insertions(+)
Hi Antonio, many thanks for your patch. Nice improvement for better filtering supported modes... Acked-by: Philippe Cornu <philippe.cornu@xxxxxxxxxxx> Reviewed-by: Philippe Cornu <philippe.cornu@xxxxxxxxxxx> Philippe :-)
