Hi Pekka
On Fri, 19 Nov 2021 at 14:31, Pekka Paalanen <ppaalanen@xxxxxxxxx> wrote:
>
> On Wed, 17 Nov 2021 15:08:58 +0100
> Maxime Ripard <maxime@xxxxxxxxxx> wrote:
>
> > From: Dave Stevenson <dave.stevenson@xxxxxxxxxxxxxxx>
> >
> > Adds a format that is 3 10bit YUV 4:2:0 samples packed into
> > a 32bit work (with 2 spare bits).
> >
> > Supported on Broadcom BCM2711 chips.
> >
> > Signed-off-by: Dave Stevenson <dave.stevenson@xxxxxxxxxxxxxxx>
> > Signed-off-by: Maxime Ripard <maxime@xxxxxxxxxx>
> > ---
> > drivers/gpu/drm/drm_fourcc.c | 3 +++
> > include/uapi/drm/drm_fourcc.h | 11 +++++++++++
> > 2 files changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> > index 25837b1d6639..07741b678798 100644
> > --- a/drivers/gpu/drm/drm_fourcc.c
> > +++ b/drivers/gpu/drm/drm_fourcc.c
> > @@ -269,6 +269,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
> > .num_planes = 3, .char_per_block = { 2, 2, 2 },
> > .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0,
> > .vsub = 0, .is_yuv = true },
> > + { .format = DRM_FORMAT_P030, .depth = 0, .num_planes = 2,
> > + .char_per_block = { 4, 8, 0 }, .block_w = { 3, 3, 0 }, .block_h = { 1, 1, 0 },
> > + .hsub = 2, .vsub = 2, .is_yuv = true},
> > };
> >
> > unsigned int i;
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index 7f652c96845b..2e6d2ecae45f 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -330,6 +330,13 @@ extern "C" {
> > */
> > #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
> >
> > +/*
> > + * 2 plane YCbCr MSB aligned, 3 pixels packed into 4 bytes.
>
> Hi,
>
> what does "MSB aligned" mean? How widely used term is that?
DRM_FORMAT_P210, DRM_FORMAT_P010, DRM_FORMAT_P012, and DRM_FORMAT_P016
all use it in drm_fourcc.h
https://github.com/torvalds/linux/blob/master/include/uapi/drm/drm_fourcc.h#L290
> > + * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
>
> Because if I had to say, this looks like LSB aligned?
>
> > + * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
>
> And this is not really either, I guess.
Yup, looks like I was a bit too keen on copy/paste from the Intel formats :-(
/* 2 plane YCbCr420.
* 3 10 bit components and 2 padding bits packed into 4 bytes.
* index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
* index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0
[2:10:10:10:2:10:10:10] little endian
*/
Dave
> Thanks,
> pq
>
> > + */
> > +#define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
> > +
> > /*
> > * 3 plane YCbCr
> > * index 0: Y plane, [7:0] Y
> > @@ -854,6 +861,10 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
> > * and UV. Some SAND-using hardware stores UV in a separate tiled
> > * image from Y to reduce the column height, which is not supported
> > * with these modifiers.
> > + *
> > + * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also
> > + * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes
> > + * wide, but as this is a 10 bpp format that translates to 96 pixels.
> > */
> >
> > #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
>
