On Tue, 23 Nov 2021 at 16:39, Bjorn Andersson
<bjorn.andersson@xxxxxxxxxx> wrote:
>
> In addition to the other 7xxx INTF interrupt regions, SM8350 has
> additional INTF regions at 0x0ae37000, 0x0ae38000 and 0x0ae39000, define
> these. The 7xxx naming scheme of the bits are kept for consistency.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 ++++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 3 +++
> 2 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index d2b6dca487e3..a77a5eaa78ad 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -30,6 +30,9 @@
> #define MDP_AD4_INTR_STATUS_OFF 0x420
> #define MDP_INTF_0_OFF_REV_7xxx 0x34000
> #define MDP_INTF_1_OFF_REV_7xxx 0x35000
> +#define MDP_INTF_2_OFF_REV_7xxx 0x36000
> +#define MDP_INTF_3_OFF_REV_7xxx 0x37000
> +#define MDP_INTF_4_OFF_REV_7xxx 0x38000
> #define MDP_INTF_5_OFF_REV_7xxx 0x39000
>
> /**
> @@ -110,6 +113,21 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
> MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_EN,
> MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_STATUS
> },
> + {
> + MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_CLEAR,
> + MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_EN,
> + MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_STATUS
> + },
> + {
> + MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_CLEAR,
> + MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_EN,
> + MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_STATUS
> + },
> + {
> + MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_CLEAR,
> + MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_EN,
> + MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_STATUS
> + },
> {
> MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_CLEAR,
> MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index d50e78c9f148..1ab75cccd145 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -26,6 +26,9 @@ enum dpu_hw_intr_reg {
> MDP_AD4_1_INTR,
> MDP_INTF0_7xxx_INTR,
> MDP_INTF1_7xxx_INTR,
> + MDP_INTF2_7xxx_INTR,
> + MDP_INTF3_7xxx_INTR,
> + MDP_INTF4_7xxx_INTR,
> MDP_INTF5_7xxx_INTR,
> MDP_INTR_MAX,
> };
Reviewed-by: Robert Foss <robert.foss@xxxxxxxxxx>
