Hi Chun-Kuang, Thanks for the review. On Sat, 2021-10-16 at 07:37 +0800, Chun-Kuang Hu wrote: > Hi, Nancy: > > Nancy.Lin <nancy.lin@xxxxxxxxxxxx> 於 2021年10月4日 週一 下午2:21寫道： > > > > Add vdosys1 ETHDR definition. > > > > Signed-off-by: Nancy.Lin <nancy.lin@xxxxxxxxxxxx> > > --- > > .../display/mediatek/mediatek,ethdr.yaml | 145 > > ++++++++++++++++++ > > 1 file changed, 145 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y > > aml > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr > > .yaml > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr > > .yaml > > new file mode 100644 > > index 000000000000..e127f0b392d0 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr > > .yaml > > @@ -0,0 +1,145 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml*__;Iw!!CTRNKA9wMg0ARbw!y6Q5VtKDLZHoYN5bEe_S_yTm7kWd_rwPjidk5R6NBVLXVIMVYK4VVXWslRmbyBny$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!y6Q5VtKDLZHoYN5bEe_S_yTm7kWd_rwPjidk5R6NBVLXVIMVYK4VVXWslYl8ES2J$ > > > > + > > +title: Mediatek Ethdr Device Tree Bindings > > + > > +maintainers: > > + - Chun-Kuang Hu <chunkuang.hu@xxxxxxxxxx> > > + - Philipp Zabel <p.zabel@xxxxxxxxxxxxxx> > > + > > +description: | > > + ETHDR is designed for HDR video and graphics conversion in the > > external display path. > > + It handles multiple HDR input types and performs tone mapping, > > color space/color > > + format conversion, and then combine different layers, output the > > required HDR or > > + SDR signal to the subsequent display path. This engine is > > composed of two video > > + frontends, two graphic frontends, one video backend and a mixer. > > + > > +properties: > > + compatible: > > + items: > > + - const: mediatek,mt8195-disp-ethdr > > + reg: > > + maxItems: 7 > > + reg-names: > > + items: > > + - const: mixer > > + - const: vdo_fe0 > > + - const: vdo_fe1 > > + - const: gfx_fe0 > > + - const: gfx_fe1 > > + - const: vdo_be > > + - const: adl_ds > > + interrupts: > > + minItems: 1 > > + iommus: > > + description: The compatible property is DMA function blocks. > > + Should point to the respective IOMMU block with master port > > as argument, > > + see > > Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for > > + details. > > In description, you does not mention that ethdr has dma function. I > expect that video front end and graphics front end direct link to > another hardware function block and no dma function. If it has both > direct link and dma function, add explain in description. > There is DMA hardware inside the ETHDR engine, which are DS and ADL. The two engines can read hardware reg settings from dram and then apply the settings during the v-blanking period. I will explain it in description. Regards, Nancy > > + minItems: 1 > > + maxItems: 2 > > + clocks: > > + items: > > + - description: mixer clock > > + - description: video frontend 0 clock > > + - description: video frontend 1 clock > > + - description: graphic frontend 0 clock > > + - description: graphic frontend 1 clock > > + - description: video backend clock > > + - description: autodownload and menuload clock > > + - description: video frontend 0 async clock > > + - description: video frontend 1 async clock > > + - description: graphic frontend 0 async clock > > + - description: graphic frontend 1 async clock > > + - description: video backend async clock > > + - description: ethdr top clock > > + clock-names: > > + items: > > + - const: mixer > > + - const: vdo_fe0 > > + - const: vdo_fe1 > > + - const: gfx_fe0 > > + - const: gfx_fe1 > > + - const: vdo_be > > + - const: adl_ds > > + - const: vdo_fe0_async > > + - const: vdo_fe1_async > > + - const: gfx_fe0_async > > + - const: gfx_fe1_async > > + - const: vdo_be_async > > + - const: ethdr_top > > + power-domains: > > + maxItems: 1 > > + resets: > > + maxItems: 5 > > + mediatek,gce-client-reg: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + description: The register of display function block to be set > > by gce. > > + There are 4 arguments in this property, gce node, subsys id, > > offset and > > + register size. The subsys id is defined in the gce header of > > each chips > > + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the > > register of > > + display function block. > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-names > > + - interrupts > > + - power-domains > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + > > + disp_ethdr@1c114000 { > > + compatible = "mediatek,mt8195-disp-ethdr"; > > + reg = <0 0x1c114000 0 0x1000>, > > + <0 0x1c115000 0 0x1000>, > > + <0 0x1c117000 0 0x1000>, > > + <0 0x1c119000 0 0x1000>, > > + <0 0x1c11A000 0 0x1000>, > > + <0 0x1c11B000 0 0x1000>, > > + <0 0x1c11C000 0 0x1000>; > > + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", > > "gfx_fe1", > > + "vdo_be", "adl_ds"; > > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX > > 0x4000 0x1000>, > > + <&gce1 SUBSYS_1c11XXXX > > 0x5000 0x1000>, > > + <&gce1 SUBSYS_1c11XXXX > > 0x7000 0x1000>, > > + <&gce1 SUBSYS_1c11XXXX > > 0x9000 0x1000>, > > + <&gce1 SUBSYS_1c11XXXX > > 0xA000 0x1000>, > > + <&gce1 SUBSYS_1c11XXXX > > 0xB000 0x1000>, > > + <&gce1 SUBSYS_1c11XXXX > > 0xC000 0x1000>; > > + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, > > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, > > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, > > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, > > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, > > + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, > > + <&vdosys1 CLK_VDO1_26M_SLOW>, > > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, > > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, > > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, > > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, > > + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, > > + <&topckgen CLK_TOP_ETHDR_SEL>; > > + clock-names = "mixer", "vdo_fe0", "vdo_fe1", > > "gfx_fe0", "gfx_fe1", > > + "vdo_be", "adl_ds", "vdo_fe0_async", > > "vdo_fe1_async", > > + "gfx_fe0_async", > > "gfx_fe1_async","vdo_be_async", > > + "ethdr_top"; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > > + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, > > + <&iommu_vpp M4U_PORT_L3_HDR_ADL>; > > + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* > > disp mixer */ > > + resets = <&vdosys1 > > MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, > > + <&vdosys1 > > MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, > > + <&vdosys1 > > MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, > > + <&vdosys1 > > MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, > > + <&vdosys1 > > MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; > > + }; > > + > > +... > > -- > > 2.18.0 > >
