Hi Marek, On Sat, Oct 16, 2021 at 11:04:02PM +0200, Marek Vasut wrote: > Current code always sets reset line low in .pre_enable callback and > holds it low for 10ms. This is sub-optimal and increases the time > between enablement of the DSI83 and valid LVDS clock. > > Rework the reset handling such that the reset line is held low for 10ms > both in probe() of the driver and .disable callback, which guarantees > that the reset line was always held low for more than 10ms and therefore > the reset line timing requirement is satisfied. Furthermore, move the > reset handling into .enable callback so the entire DSI83 initialization > is now in one place. > > This reduces DSI83 enablement delay by up to 10ms. > > Signed-off-by: Marek Vasut <marex@xxxxxxx> > Cc: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> > Cc: Linus Walleij <linus.walleij@xxxxxxxxxx> > Cc: Robert Foss <robert.foss@xxxxxxxxxx> > Cc: Sam Ravnborg <sam@xxxxxxxxxxxx> > Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx Applied to drm-misc-next, Sam
