Hi Nathan,
On Tue, 21 Sep 2021 15:58:23 -0700 Nathan Chancellor <nathan@xxxxxxxxxx> wrote:
>
> On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote:
> > DP 2.0 brings some new DPCD addresses for PHY repeaters.
> >
> > Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx
> > Reviewed-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> > Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> > ---
> > include/drm/drm_dp_helper.h | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index 1d5b3dbb6e56..f3a61341011d 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -1319,6 +1319,10 @@ struct drm_panel;
> > #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
> > #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
> > #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
> > +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
> > +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
> > +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */
> > +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
> >
> > enum drm_dp_phy {
> > DP_PHY_DPRX,
> > --
> > 2.30.2
> >
> >
>
> This patch causes a build failure in -next when combined with the AMD
> tree:
>
> In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33:
> In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70:
> In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36:
> ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined]
> #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
> ^
> ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here
> #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
> ^
> 1 error generated.
>
> Perhaps something like this should be applied during the merge of the
> second tree or maybe this patch should be in a branch that could be
> shared between the Intel and AMD trees so that this diff could be
> applied to the AMD tree directly? Not sure what the standard procedure
> for this is.
>
> Cheers,
> Nathan
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index 234dfbea926a..279863b5c650 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -4590,7 +4590,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
> DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
>
> link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
> - lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES -
> + lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
> DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
> #endif
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> index a5e798b5da79..8caf9af5ffa2 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> @@ -878,8 +878,6 @@ struct psr_caps {
> # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
> # define DP_DSC_DECODER_COUNT_SHIFT 5
> #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
> -#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
> -#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007
> #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022
> #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
> /* TODO - Use DRM header to replace above once available */
Thanks for the heads up. I have applied the above as a merge fix patch
until something else happens.
--
Cheers,
Stephen Rothwell
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