Hi Chun-Kuang, Thanks for the review. On Fri, 2021-08-20 at 23:43 +0800, Chun-Kuang Hu wrote: > Hi, Jason: > > jason-jh.lin <jason-jh.lin@xxxxxxxxxxxx> 於 2021年8月19日 週四 上午10:23寫道： > > > > Add MERGE engine file: > > MERGE module is used to merge two slice-per-line inputs > > into one side-by-side output. > > > > Signed-off-by: jason-jh.lin <jason-jh.lin@xxxxxxxxxxxx> > > --- > > drivers/gpu/drm/mediatek/Makefile | 1 + > > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 + > > drivers/gpu/drm/mediatek/mtk_disp_merge.c | 268 > > ++++++++++++++++++++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 16 ++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 + > > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + > > 7 files changed, 297 insertions(+) > > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c > > > > diff --git a/drivers/gpu/drm/mediatek/Makefile > > b/drivers/gpu/drm/mediatek/Makefile > > index dc54a7a69005..538e0087a44c 100644 > > --- a/drivers/gpu/drm/mediatek/Makefile > > +++ b/drivers/gpu/drm/mediatek/Makefile > > @@ -3,6 +3,7 @@ > > mediatek-drm-y := mtk_disp_ccorr.o \ > > mtk_disp_color.o \ > > mtk_disp_gamma.o \ > > + mtk_disp_merge.o \ > > mtk_disp_ovl.o \ > > mtk_disp_rdma.o \ > > mtk_drm_crtc.o \ > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > > index cafd9df2d63b..f407cd9d873e 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > > @@ -46,6 +46,14 @@ void mtk_gamma_set_common(void __iomem *regs, > > struct drm_crtc_state *state); > > void mtk_gamma_start(struct device *dev); > > void mtk_gamma_stop(struct device *dev); > > > > +int mtk_merge_clk_enable(struct device *dev); > > +void mtk_merge_clk_disable(struct device *dev); > > +void mtk_merge_config(struct device *dev, unsigned int width, > > + unsigned int height, unsigned int vrefresh, > > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); > > +void mtk_merge_start(struct device *dev); > > +void mtk_merge_stop(struct device *dev); > > + > > void mtk_ovl_bgclr_in_on(struct device *dev); > > void mtk_ovl_bgclr_in_off(struct device *dev); > > void mtk_ovl_bypass_shadow(struct device *dev); > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c > > b/drivers/gpu/drm/mediatek/mtk_disp_merge.c > > new file mode 100644 > > index 000000000000..ebcb646bde9c > > --- /dev/null > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c > > @@ -0,0 +1,268 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2021 MediaTek Inc. > > + */ > > + > > +#include <linux/clk.h> > > +#include <linux/component.h> > > +#include <linux/of_device.h> > > +#include <linux/of_irq.h> > > +#include <linux/platform_device.h> > > +#include <linux/soc/mediatek/mtk-cmdq.h> > > + > > +#include "mtk_drm_ddp_comp.h" > > +#include "mtk_drm_drv.h" > > +#include "mtk_disp_drv.h" > > + > > +#define DISP_REG_MERGE_CTRL 0x000 > > +#define MERGE_EN 1 > > +#define DISP_REG_MERGE_CFG_0 0x010 > > +#define DISP_REG_MERGE_CFG_4 0x020 > > +#define DISP_REG_MERGE_CFG_10 0x038 > > +/* no swap */ > > +#define SWAP_MODE 0 > > +#define FLD_SWAP_MODE GENMASK(4, 0) > > +#define DISP_REG_MERGE_CFG_12 0x040 > > +#define CFG_10_10_1PI_2PO_BUF_MODE 6 > > +#define CFG_10_10_2PI_2PO_BUF_MODE 8 > > +#define FLD_CFG_MERGE_MODE GENMASK(4, 0) > > +#define DISP_REG_MERGE_CFG_24 0x070 > > +#define DISP_REG_MERGE_CFG_25 0x074 > > +#define DISP_REG_MERGE_CFG_36 0x0a0 > > +#define ULTRA_EN 1 > > You could use FLD_ULTRA_EN for this. OK, I'll use mtk_ddp_write() directly, if the bit width of setting is always the same as mask. > > > +#define PREULTRA_EN 1 > > +#define HALT_FOR_DVFS_EN 0 > > You could just not set this. OK, I'll remove the setting of 0. > > > +#define FLD_ULTRA_EN GENMASK(0, 0) > > #define FLD_ULTRA_EN BIT(0) > > Regards, > Chun-Kuang. > OK, I'll just use BIT(n) instead of GENMASK(n, n). Regards, Jason-JH.Lin > > +#define FLD_PREULTRA_EN GENMASK(4, > > 4) > > +#define FLD_HALT_FOR_DVFS_EN GENMASK(8, 8) > > +#define DISP_REG_MERGE_CFG_37 0x0a4 > > +/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */ > > +#define BUFFER_MODE 3 > > +#define FLD_BUFFER_MODE GENMASK(1, > > 0) > > +#define DISP_REG_MERGE_CFG_38 0x0a8 > > +#define FLD_VDE_BLOCK_ULTRA GENMASK(0, 0) > > +#define FLD_VALID_TH_BLOCK_ULTRA GENMASK(4, 4) > > +#define FLD_ULTRA_FIFO_VALID_TH GENMASK(31, > > 16) > > +#define DISP_REG_MERGE_CFG_39 0x0ac > > +#define FLD_NVDE_FORCE_PREULTRA GENMASK(8, > > 8) > > +#define FLD_NVALID_TH_FORCE_PREULTRA GENMASK(12, 12) > > +#define FLD_PREULTRA_FIFO_VALID_TH GENMASK(31, 16) -- Jason-JH Lin <jason-jh.lin@xxxxxxxxxxxx>
