Hi CK, On Sun, 2021-08-01 at 08:36 +0800, Chun-Kuang Hu wrote: > Hi, Jason: > > jason-jh.lin <jason-jh.lin@xxxxxxxxxxxx> 於 2021年7月30日 週五 上午1:07寫道： > > > > Add display node for vdosys0. > > > > Signed-off-by: jason-jh.lin <jason-jh.lin@xxxxxxxxxxxx> > > --- > > This patch is based on [1][2][3][4] > > > > [1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and > > Makefile > > - > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@xxxxxxxxxxxx/__;!!CTRNKA9wMg0ARbw!3bjfjGf2GYJ5FQ5EWsjG9yPGwf6uVMv8dDyXLY2Tlq_sTczeIJkEDTWVt1dxp4b7tojj$ > > > > [2]arm64: dts: mt8195: add IOMMU and smi nodes > > - > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@xxxxxxxxxxxx/__;!!CTRNKA9wMg0ARbw!3bjfjGf2GYJ5FQ5EWsjG9yPGwf6uVMv8dDyXLY2Tlq_sTczeIJkEDTWVt1dxp0sfXPc-$ > > > > [3]arm64: dts: mt8195: add gce node > > - > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210705053429.4380-4-jason-jh.lin@xxxxxxxxxxxx/__;!!CTRNKA9wMg0ARbw!3bjfjGf2GYJ5FQ5EWsjG9yPGwf6uVMv8dDyXLY2Tlq_sTczeIJkEDTWVt1dxp5uw6cqB$ > > > > [4]add mt8195 SoC DRM binding > > - > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597__;!!CTRNKA9wMg0ARbw!3bjfjGf2GYJ5FQ5EWsjG9yPGwf6uVMv8dDyXLY2Tlq_sTczeIJkEDTWVt1dxp0qn1imR$ > > > > --- > > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 112 > > +++++++++++++++++++++++ > > 1 file changed, 112 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > index 04d3e95175fa..4fa47cb2bede 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > @@ -1155,9 +1155,121 @@ > > #clock-cells = <1>; > > }; > > > > [snip] > > > + > > + merge0: disp_vpp_merge0@1c014000 { > > + compatible = "mediatek,mt8195-disp-merge"; > > + reg = <0 0x1c014000 0 0x1000>; > > + interrupts = <GIC_SPI 656 > > IRQ_TYPE_LEVEL_HIGH 0>; > > + power-domains = <&spm > > MT8195_POWER_DOMAIN_VDOSYS0>; > > + clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; > > Why this merge has no async clock? > > Regards, > Chun-Kuang. > Only the MERGE linked to the display function block that is cross vdosys0 to vdosys1 need to add async clock. I'll add this description into this patch [1] [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210729154912.20051-4-jason-jh.lin@xxxxxxxxxxxx/ Regards, Jason-JH.Lin > > + mediatek,gce-client-reg = > > + <&gce1 SUBSYS_1c01XXXX 0x4000 > > 0x1000>; > > + }; > > + -- Jason-JH Lin <jason-jh.lin@xxxxxxxxxxxx>
