Hey Doug,
Thank you for submitting this.
On Wed, 28 Jul 2021 at 18:46, Douglas Anderson <dianders@xxxxxxxxxxxx> wrote:
>
> When testing with a panel that's apparently a little more persnickety
> about the correct power sequence (specifically Samsung ATNA33XC20), we
> found that the ti-sn65dsi86 was doing things just slightly wrong.
>
> Looking closely at the ti-sn65dsi86's datasheet, the power off
> sequence is supposed to be:
> 1. Clear VSTREAM_ENABLE bit
> 2. Stop DSI stream from GPU. DSI lanes must be placed in LP11 state.
> 3. Program the ML_TX_MODE to 0x0 (OFF)
> 4. Program the DP_NUM_LANES register to 0x0
> 5. Clear the DP_PLL_EN bit.
> 6. Deassert the EN pin.
> 7. Remove power from supply pins
>
> Since we were doing the whole sequence in the "disable", I believe
> that step #2 (stopping the DSI stream from the GPU) wasn't
> happening. We also weren't setting DP_NUM_LANES to 0.
>
> Let's fix this.
>
> NOTE: things are a little asymmetric now. For instance, we turn the
> PLL on in "enable" but now we're not turning it off until
> "post_disable". It would seem to make sense to move the PLL turning on
> to "pre_enable" to match. Unfortunately, I don't believe that's
> allowed. It looks as if (in the non-refclk mode which probably nobody
> is using) we have to wait until the MIPI clock is there before we can
> enable the PLL. In any case, the way it is here won't really
> hurt--it'll just leave the PLL on a little longer.
>
> Fixes: a095f15c00e2 ("drm/bridge: add support for sn65dsi86 bridge driver")
> Signed-off-by: Douglas Anderson <dianders@xxxxxxxxxxxx>
> ---
>
> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> index 9bf889302bcc..5e932070a1c3 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -766,10 +766,6 @@ static void ti_sn_bridge_disable(struct drm_bridge *bridge)
>
> /* disable video stream */
> regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
> - /* semi auto link training mode OFF */
> - regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
> - /* disable DP PLL */
> - regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
> }
>
> static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata)
> @@ -1106,6 +1102,13 @@ static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
> {
> struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
>
> + /* semi auto link training mode OFF */
> + regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
> + /* Num lanes to 0 as per power sequencing in data sheet */
> + regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0);
> + /* disable DP PLL */
> + regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
> +
> if (!pdata->refclk)
> ti_sn65dsi86_disable_comms(pdata);
>
> --
> 2.32.0.432.gabb21c7263-goog
>
Acked-by: Robert Foss <robert.foss@xxxxxxxxxx>
