Some bridge chip will shift screen when the dsi data does't ent at the same time in line. Signed-off-by: Jitao Shi <jitao.shi@xxxxxxxxxxxx> --- .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index 8238a86686be..1c2f53f3ac3d 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -19,6 +19,10 @@ Required properties: Documentation/devicetree/bindings/graph.txt. This port should be connected to the input port of an attached DSI panel or DSI-to-eDP encoder chip. +Optional properties: +- force_dsi_end_without_null: Some bridge chip(ex. ANX7625) requires the + packets on lanes aligned at the end. + MIPI TX Configuration Module ============================ -- 2.25.1
