On 29/06/2021 04:04, Chunyou Tang wrote: > Hi Steve, > thinks for your reply. > I set the pte in arm_lpae_prot_to_pte(), > *********************************************************************** > /* > * Also Mali has its own notions of shareability wherein its > Inner > * domain covers the cores within the GPU, and its Outer domain > is > * "outside the GPU" (i.e. either the Inner or System domain in > CPU > * terms, depending on coherency). > */ > if (prot & IOMMU_CACHE && data->iop.fmt != ARM_MALI_LPAE) > pte |= ARM_LPAE_PTE_SH_IS; > else > pte |= ARM_LPAE_PTE_SH_OS; > *********************************************************************** > I set pte |= ARM_LPAE_PTE_SH_NS. > > If I set pte to ARM_LPAE_PTE_SH_OS or > ARM_LPAE_PTE_SH_IS,whether I use singel core GPU or multi core > GPU,it will occur GPU Fault. > if I set pte to ARM_LPAE_PTE_SH_NS,whether I use singel core > GPU or multi core GPU,it will not occur GPU Fault. Hi, So this is a difference between Panfrost and kbase. Panfrost (well technically the IOMMU framework) enables the inner-shareable bit for all memory, whereas kbase only enables it for some memory types (the BASE_MEM_COHERENT_LOCAL flag in the UABI controls it). However this should only be a performance/power difference (and AFAIK probably an irrelevant one) and it's definitely required that "inner shareable" (i.e. within the GPU) works for communication between the different units of the GPU. You didn't answer my previous question: > Is this device working with the kbase/DDK proprietary driver? What you are describing sounds like a hardware integration issue, so it would be good to check that the hardware is working with the proprietary driver to rule that out. And perhaps there is something in the kbase for this device that is setting a chicken bit to 'fix' the coherency? Steve
