On Mon, 2021-06-28 at 18:53 +0000, Ruhl, Michael J wrote:
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf
> > Of
> > Thomas Hellström
> > Sent: Monday, June 28, 2021 10:46 AM
> > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx;
> > dri-devel@xxxxxxxxxxxxxxxxxxxxx
> > Cc: Thomas Hellström <thomas.hellstrom@xxxxxxxxxxxxxxx>; Auld,
> > Matthew
> > <matthew.auld@xxxxxxxxx>
> > Subject: [Intel-gfx] [PATCH v3 2/5] drm/i915/gem: Introduce a
> > selftest for the
> > gem object migrate functionality
> >
> > From: Matthew Auld <matthew.auld@xxxxxxxxx>
> >
> > A selftest for the gem object migrate functionality. Slightly
> > adapted
> > from the original by Matthew to the new interface and new fill blit
> > code.
> >
> > Co-developed-by: Thomas Hellström
> > <thomas.hellstrom@xxxxxxxxxxxxxxx>
> > Signed-off-by: Thomas Hellström <thomas.hellstrom@xxxxxxxxxxxxxxx>
> > Signed-off-by: Matthew Auld <matthew.auld@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_object.c | 1 +
> > .../drm/i915/gem/selftests/i915_gem_migrate.c | 237
> > ++++++++++++++++++
> > .../drm/i915/selftests/i915_live_selftests.h | 1 +
> > 3 files changed, 239 insertions(+)
> > create mode 100644
> > drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > index 1c18be067b58..ff147fd59874 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > @@ -649,6 +649,7 @@ static const struct drm_gem_object_funcs
> > i915_gem_object_funcs = {
> > #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> > #include "selftests/huge_gem_object.c"
> > #include "selftests/huge_pages.c"
> > +#include "selftests/i915_gem_migrate.c"
> > #include "selftests/i915_gem_object.c"
> > #include "selftests/i915_gem_coherency.c"
> > #endif
> > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c
> > b/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c
> > new file mode 100644
> > index 000000000000..a437b66f64d9
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c
> > @@ -0,0 +1,237 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2020-2021 Intel Corporation
> > + */
> > +
> > +#include "gt/intel_migrate.h"
> > +
> > +static int igt_smem_create_migrate(void *arg)
> > +{
> > + struct intel_gt *gt = arg;
> > + struct drm_i915_private *i915 = gt->i915;
> > + struct drm_i915_gem_object *obj;
> > + struct i915_gem_ww_ctx ww;
> > + int err = 0;
> > +
> > + /* Switch object backing-store on create */
> > + obj = i915_gem_object_create_lmem(i915, PAGE_SIZE, 0);
> > + if (IS_ERR(obj))
> > + return PTR_ERR(obj);
> > +
> > + for_i915_gem_ww(&ww, err, true) {
> > + err = i915_gem_object_lock(obj, &ww);
> > + if (err)
> > + continue;
> > +
> > + if (!i915_gem_object_can_migrate(obj,
> > INTEL_REGION_SMEM)) {
> > + err = -EINVAL;
> > + continue;
> > + }
> > +
> > + err = i915_gem_object_migrate(obj, &ww,
> > INTEL_REGION_SMEM);
> > + if (err)
> > + continue;
> > +
> > + err = i915_gem_object_pin_pages(obj);
> > + if (err)
> > + continue;
> > +
> > + if (i915_gem_object_can_migrate(obj,
> > INTEL_REGION_LMEM))
> > + err = -EINVAL;
> > +
> > + i915_gem_object_unpin_pages(obj);
> > + }
> > + i915_gem_object_put(obj);
> > +
> > + return err;
> > +}
> > +
> > +static int igt_lmem_create_migrate(void *arg)
> > +{
> > + struct intel_gt *gt = arg;
> > + struct drm_i915_private *i915 = gt->i915;
> > + struct drm_i915_gem_object *obj;
> > + struct i915_gem_ww_ctx ww;
> > + int err = 0;
> > +
> > + /* Switch object backing-store on create */
> > + obj = i915_gem_object_create_shmem(i915, PAGE_SIZE);
> > + if (IS_ERR(obj))
> > + return PTR_ERR(obj);
> > +
> > + for_i915_gem_ww(&ww, err, true) {
> > + err = i915_gem_object_lock(obj, &ww);
> > + if (err)
> > + continue;
> > +
> > + if (!i915_gem_object_can_migrate(obj,
> > INTEL_REGION_LMEM)) {
> > + err = -EINVAL;
> > + continue;
> > + }
> > +
> > + err = i915_gem_object_migrate(obj, &ww,
> > INTEL_REGION_LMEM);
> > + if (err)
> > + continue;
> > +
> > + err = i915_gem_object_pin_pages(obj);
> > + if (err)
> > + continue;
> > +
> > + if (i915_gem_object_can_migrate(obj,
> > INTEL_REGION_SMEM))
> > + err = -EINVAL;
> > +
> > + i915_gem_object_unpin_pages(obj);
> > + }
> > + i915_gem_object_put(obj);
> > +
> > + return err;
> > +}
> > +
> > +static int lmem_pages_migrate_one(struct i915_gem_ww_ctx *ww,
> > + struct drm_i915_gem_object *obj)
> > +{
> > + int err;
> > +
> > + err = i915_gem_object_lock(obj, ww);
> > + if (err)
> > + return err;
> > +
> > + err = i915_gem_object_wait(obj,
> > + I915_WAIT_INTERRUPTIBLE |
> > + I915_WAIT_PRIORITY |
> > + I915_WAIT_ALL,
> > + MAX_SCHEDULE_TIMEOUT);
> > + if (err)
> > + return err;
> > +
> > + if (i915_gem_object_is_lmem(obj)) {
> > + if (!i915_gem_object_can_migrate(obj,
> > INTEL_REGION_SMEM)) {
>
> I don't see any testing of the parameter num_allowed.
>
> Is that done somewhere else?
>
> Mike
That's a user-space submitted parameter only, dictating what region the
object is allowed in when bound to the GPU. It's not exercised in this
selftest.
Thanks,
Thomas
