Re: [PATCH 3/3] drm/i915/gtt: ignore min_page_size for paging structures

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On 6/23/21 1:26 PM, Matthew Auld wrote:
The min_page_size is only needed for pages inserted into the GTT, and
for our paging structures we only need at most 4K bytes, so simply
ignore the min_page_size restrictions here, otherwise we might see some
severe overallocation on some devices.

Signed-off-by: Matthew Auld <matthew.auld@xxxxxxxxx>
Cc: Thomas Hellström <thomas.hellstrom@xxxxxxxxxxxxxxx>
---
  drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 084ea65d59c0..61e8a8c25374 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -16,7 +16,7 @@ struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz)
  {
  	struct drm_i915_gem_object *obj;
- obj = i915_gem_object_create_lmem(vm->i915, sz, 0);
+	obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 0);
  	/*
  	 * Ensure all paging structures for this vm share the same dma-resv
  	 * object underneath, with the idea that one object_lock() will lock

I think for this one the new gt migration code might break, because there we insert even PT pages into the GTT, so it might need a special interface? Ram is looking at supporter larger GPU PTE sizes with that code..

/Thomas






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