On Mon, Jun 21, 2021 at 2:25 AM Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx> wrote:
>
> Add MIPI DSI pipeline for i.MX8MM.
>
> Video pipeline start from eLCDIF to MIPI DSI and respective
> Panel or Bridge on the backend side.
>
> Add support for it.
>
> Cc: Rob Herring <robh+dt@xxxxxxxxxx>
> Signed-off-by: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 59 +++++++++++++++++++++++
> 1 file changed, 59 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 5f68182ed3a6..bc09fce0f6a9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1047,6 +1047,65 @@ lcdif: lcdif@32e00000 {
> interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_LCDIF>;
> status = "disabled";
> +
> + port {
> + lcdif_out_dsi: endpoint {
> + remote-endpoint = <&dsi_in_lcdif>;
> + };
> + };
> + };
> +
> + dsi: dsi@32e10000 {
> + compatible = "fsl,imx8mm-sec-dsim";
> + reg = <0x32e10000 0xa0>;
> + clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> + <&clk IMX8MM_CLK_DSI_PHY_REF>;
> + clock-names = "bus", "phy_ref";
> + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> + <&clk IMX8MM_VIDEO_PLL1_OUT>,
> + <&clk IMX8MM_CLK_DSI_PHY_REF>;
> + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
> + <&clk IMX8MM_VIDEO_PLL1_BYPASS>,
> + <&clk IMX8MM_VIDEO_PLL1_OUT>;
> + assigned-clock-rates = <266000000>, <594000000>, <27000000>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&dphy>;
> + phy-names = "dphy";
> + power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DSI>;
> + samsung,burst-clock-frequency = <891000000>;
> + samsung,esc-clock-frequency = <54000000>;
> + samsung,pll-clock-frequency = <27000000>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dsi_in_lcdif: endpoint@0 {
> + reg = <0>;
When I build this with W=1, I get a warning:
Warning (graph_child_address):
/soc@0/bus@32c00000/dsi@32e10000/ports/port@0: graph node has single
child node 'endpoint@0', #address-cells/#size-cells are not necessary
Are there supposed to be two endpoints for port@0?
> + remote-endpoint = <&lcdif_out_dsi>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> + dphy: dphy@32e100a4 {
> + compatible = "fsl,imx8mm-sec-dsim-dphy";
> + reg = <0x32e100a4 0xbc>;
> + clocks = <&clk IMX8MM_CLK_DSI_PHY_REF>;
> + clock-names = "phy_ref";
> + #phy-cells = <0>;
> + power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DPHY>;
> + status = "disabled";
> };
>
> dispmix_blk_ctl: blk-ctl@32e28000 {
> --
> 2.25.1
>
