+
+ return ret;
+}
+
+static ssize_t
+i915_power1_max_enable_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_i915_private *i915 = dev_get_drvdata(dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ intel_wakeref_t wakeref;
+ ssize_t ret;
+ u32 reg_value;
+ bool is_enabled;
+
+ with_intel_runtime_pm(uncore->rpm, wakeref)
+ reg_value = intel_uncore_read(uncore,
+ i915->hwmon.rg.pkg_rapl_limit);
+
+ is_enabled = !!(reg_value & PKG_PWR_LIM_1_EN);
+
+ ret = sysfs_emit(buf, "%u\n", is_enabled);
+
+ return ret;
+}
+
+static ssize_t
+i915_power1_max_interval_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_i915_private *i915 = dev_get_drvdata(dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ struct i915_hwmon *hwmon = &i915->hwmon;
+ ssize_t ret;
+ u64 ullval;
+
+ ullval = _field_read_and_scale(uncore, hwmon->rg.pkg_rapl_limit,
+ PKG_PWR_LIM_1_TIME,
+ FIELD_SHIFT(PKG_PWR_LIM_1_TIME),
+ hwmon->scl_shift_time, SF_TIME);
+
+ ret = sysfs_emit(buf, "%llu\n", ullval);
+
+ return ret;
+}
+
+static ssize_t
+i915_power1_max_interval_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct drm_i915_private *i915 = dev_get_drvdata(dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ struct i915_hwmon *hwmon = &i915->hwmon;
+ ssize_t ret;
+ long val;
+
+ ret = kstrtoul(buf, 0, &val);
+ if (ret)
+ return ret;
+
+ _field_scale_and_write(uncore, hwmon->rg.pkg_rapl_limit,
+ PKG_PWR_LIM_2_TIME,
+ FIELD_SHIFT(PKG_PWR_LIM_2_TIME),
+ hwmon->scl_shift_time, SF_TIME, val);
+
+ return count;
+}
+
+static ssize_t
+i915_power1_cap_enable_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_i915_private *i915 = dev_get_drvdata(dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ struct i915_hwmon *hwmon = &i915->hwmon;
+ intel_wakeref_t wakeref;
+ ssize_t ret;
+ u32 reg_value;
+ bool is_enabled;
+
+ with_intel_runtime_pm(uncore->rpm, wakeref)
+ reg_value = intel_uncore_read(uncore,
+ hwmon->rg.pkg_rapl_limit_udw);
+
+ is_enabled = !!(reg_value & PKG_PWR_LIM_2_EN);
+
+ ret = sysfs_emit(buf, "%u\n", is_enabled);
+
+ return ret;
+}
+
+static ssize_t
+i915_power1_cap_enable_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct drm_i915_private *i915 = dev_get_drvdata(dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ struct i915_hwmon *hwmon = &i915->hwmon;
+ ssize_t ret;
+ u32 val;
+ u32 bits_to_clear;
+ u32 bits_to_set;
+
+ ret = kstrtou32(buf, 0, &val);
+ if (ret)
+ return ret;
+
+ bits_to_clear = PKG_PWR_LIM_2_EN;
+ if (!val)
+ bits_to_set = 0;
+ else
+ bits_to_set = PKG_PWR_LIM_2_EN;
+
+ _locked_with_pm_intel_uncore_rmw(uncore, hwmon->rg.pkg_rapl_limit_udw,
+ bits_to_clear, bits_to_set);
+
+ return count;
+}
+
+static ssize_t
+i915_power_default_limit_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_i915_private *i915 = dev_get_drvdata(dev);
+ struct i915_hwmon *hwmon = &i915->hwmon;
+ ssize_t ret;
+
+ ret = sysfs_emit(buf, "%u\n", hwmon->power_max_initial_value);
+
+ return ret;
+}
+
+static ssize_t
+i915_power_min_limit_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_i915_private *i915 = dev_get_drvdata(dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ struct i915_hwmon *hwmon = &i915->hwmon;
+ ssize_t ret;
+ u32 uval;
+
+ /*
+ * This is a 64-bit register but the individual fields are under 32 bits
+ * in size even after scaling.
+ * The UAPI specifies a size of 32 bits.
+ * The UAPI specifies that 0 should be returned if unsupported.
+ * So, using u32 and %u is sufficient.
+ */
+ if (i915_mmio_reg_valid(hwmon->rg.pkg_power_sku))
+ uval = (u32)_field_read64_and_scale(uncore,
+ hwmon->rg.pkg_power_sku,
+ PKG_MIN_PWR,
+ FIELD_SHIFT(PKG_MIN_PWR),
+ hwmon->scl_shift_power,
+ SF_POWER);
+ else
+ uval = 0;
+
+ ret = sysfs_emit(buf, "%u\n", uval);
+
+ return ret;
+}
+
+static ssize_t
+i915_power_max_limit_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_i915_private *i915 = dev_get_drvdata(dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ struct i915_hwmon *hwmon = &i915->hwmon;
+ ssize_t ret;
+ u32 uval;
+
+ /*
+ * This is a 64-bit register but the individual fields are under 32 bits
+ * in size even after scaling.
+ * The UAPI specifies a size of 32 bits.
+ * The UAPI specifies that UINT_MAX should be returned if unsupported.
+ * So, using u32 and %u is sufficient.
+ */
+ if (i915_mmio_reg_valid(hwmon->rg.pkg_power_sku))
+ uval = (u32)_field_read64_and_scale(uncore,
+ hwmon->rg.pkg_power_sku,
+ PKG_MAX_PWR,
+ FIELD_SHIFT(PKG_MAX_PWR),
+ hwmon->scl_shift_power,
+ SF_POWER);
+ else
+ uval = UINT_MAX;
+
+ ret = sysfs_emit(buf, "%u\n", uval);
+
+ return ret;
+}
+
+static SENSOR_DEVICE_ATTR(power1_max_enable, 0444,
+ i915_power1_max_enable_show, NULL, 0);
+static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
+ i915_power1_max_interval_show,
+ i915_power1_max_interval_store, 0);
+static SENSOR_DEVICE_ATTR(power1_cap_enable, 0664,
+ i915_power1_cap_enable_show,
+ i915_power1_cap_enable_store, 0);
+static SENSOR_DEVICE_ATTR(power_default_limit, 0444,
+ i915_power_default_limit_show, NULL, 0);
+static SENSOR_DEVICE_ATTR(power_min_limit, 0444,
+ i915_power_min_limit_show, NULL, 0);
+static SENSOR_DEVICE_ATTR(power_max_limit, 0444,
+ i915_power_max_limit_show, NULL, 0);
+static SENSOR_DEVICE_ATTR(energy1_input, 0444,
+ i915_energy1_input_show, NULL, 0);
+
+static struct attribute *hwmon_attributes[] = {
+ &sensor_dev_attr_power1_max_enable.dev_attr.attr,
+ &sensor_dev_attr_power1_max_interval.dev_attr.attr,
+ &sensor_dev_attr_power1_cap_enable.dev_attr.attr,
+ &sensor_dev_attr_power_default_limit.dev_attr.attr,
+ &sensor_dev_attr_power_min_limit.dev_attr.attr,
+ &sensor_dev_attr_power_max_limit.dev_attr.attr,
+ &sensor_dev_attr_energy1_input.dev_attr.attr,
+ NULL
+};
+
+static umode_t hwmon_attributes_visible(struct kobject *kobj,
+ struct attribute *attr, int index)
+{
+ struct device *dev = kobj_to_dev(kobj);
+ struct drm_i915_private *i915 = dev_get_drvdata(dev);
+ struct i915_hwmon *hwmon = &i915->hwmon;
+ i915_reg_t rgadr;
+
+ if (attr == &sensor_dev_attr_energy1_input.dev_attr.attr)
+ rgadr = hwmon->rg.pkg_energy_status;
+ else if (attr == &sensor_dev_attr_power1_max_enable.dev_attr.attr)
+ rgadr = hwmon->rg.pkg_rapl_limit;
+ else if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr)
+ rgadr = hwmon->rg.pkg_rapl_limit;
+ else if (attr == &sensor_dev_attr_power1_cap_enable.dev_attr.attr)
+ rgadr = hwmon->rg.pkg_rapl_limit_udw;
+ else if (attr == &sensor_dev_attr_power_default_limit.dev_attr.attr)
+ rgadr = hwmon->rg.pkg_rapl_limit;
+ else if (attr == &sensor_dev_attr_power_min_limit.dev_attr.attr)
+ return attr->mode;
+ else if (attr == &sensor_dev_attr_power_max_limit.dev_attr.attr)
+ return attr->mode;
+ else
+ return 0;
+
+ if (!i915_mmio_reg_valid(rgadr))
+ return 0;
+
+ return attr->mode;
+}
+
+static const struct attribute_group hwmon_attrgroup = {
+ .attrs = hwmon_attributes,
+ .is_visible = hwmon_attributes_visible,
+};
+
+static const struct attribute_group *hwmon_groups[] = {
+ &hwmon_attrgroup,
+ NULL
+};
+
+/*
+ * HWMON SENSOR TYPE = hwmon_power
+ * - Sustained Power (power1_max)
+ * - Burst power (power1_cap)
+ * - Peak power (power1_crit)
+ */
+static const u32 i915_config_power[] = {
+ HWMON_P_CAP | HWMON_P_MAX,
+ 0
+};
+
+static const struct hwmon_channel_info i915_power = {
+ .type = hwmon_power,
+ .config = i915_config_power,
+};
+
+static const struct hwmon_channel_info *i915_info[] = {
+ &i915_power,
+ NULL
+};
+
+static umode_t
+i915_power_is_visible(const struct drm_i915_private *i915, u32 attr, int chan)
+{
+ i915_reg_t rgadr;
+
+ switch (attr) {
+ case hwmon_power_max:
+ rgadr = i915->hwmon.rg.pkg_rapl_limit;
+ break;
+ case hwmon_power_cap:
+ rgadr = i915->hwmon.rg.pkg_rapl_limit_udw;
+ break;
+ default:
+ return 0;
+ }
+
+ if (!i915_mmio_reg_valid(rgadr))
+ return 0;
+
+ return 0664;
+}
+
+static int
+i915_power_read(struct drm_i915_private *i915, u32 attr, int chan, long *val)
+{
+ struct intel_uncore *uncore = &i915->uncore;
+ struct i915_hwmon *hwmon = &i915->hwmon;
+ int ret = 0;
+
+ switch (attr) {
+ case hwmon_power_max:
+ *val = (long)_field_read_and_scale(uncore,
+ hwmon->rg.pkg_rapl_limit,
+ PKG_PWR_LIM_1,
+ FIELD_SHIFT(PKG_PWR_LIM_1),
+ hwmon->scl_shift_power,
+ SF_POWER);
+ break;
+ case hwmon_power_cap:
+ *val = (long)_field_read_and_scale(uncore,
+ hwmon->rg.pkg_rapl_limit_udw,
+ PKG_PWR_LIM_2,
+ FIELD_SHIFT(PKG_PWR_LIM_2),
+ hwmon->scl_shift_power,
+ SF_POWER);
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ }
+
+ return ret;
+}
+
+static int
+i915_power_write(struct drm_i915_private *i915, u32 attr, int chan, long val)
+{
+ struct intel_uncore *uncore = &i915->uncore;
+ struct i915_hwmon *hwmon = &i915->hwmon;
+ int ret = 0;
+
+ switch (attr) {
+ case hwmon_power_max:
+ _field_scale_and_write(uncore,
+ hwmon->rg.pkg_rapl_limit,
+ PKG_PWR_LIM_1,
+ FIELD_SHIFT(PKG_PWR_LIM_1),
+ hwmon->scl_shift_power,
+ SF_POWER, val);
+ break;
+ case hwmon_power_cap:
+ _field_scale_and_write(uncore,
+ hwmon->rg.pkg_rapl_limit_udw,
+ PKG_PWR_LIM_2,
+ FIELD_SHIFT(PKG_PWR_LIM_2),
+ hwmon->scl_shift_power,
+ SF_POWER, val);
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ }
+
+ return ret;
+}
+
+static umode_t
+i915_is_visible(const void *data, enum hwmon_sensor_types type,
+ u32 attr, int channel)
+{
+ struct drm_i915_private *i915 = (struct drm_i915_private *)data;
+
+ switch (type) {
+ case hwmon_power:
+ return i915_power_is_visible(i915, attr, channel);
+ default:
+ return 0;
+ }
+}
+
+static int
+i915_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
+ int channel, long *val)
+{
+ struct drm_i915_private *i915 = kdev_to_i915(dev);
+
+ switch (type) {
+ case hwmon_power:
+ return i915_power_read(i915, attr, channel, val);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int
+i915_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
+ int channel, long val)
+{
+ struct drm_i915_private *i915 = kdev_to_i915(dev);
+
+ switch (type) {
+ case hwmon_power:
+ return i915_power_write(i915, attr, channel, val);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static const struct hwmon_ops i915_hwmon_ops = {
+ .is_visible = i915_is_visible,
+ .read = i915_read,
+ .write = i915_write,
+};
+
+static const struct hwmon_chip_info i915_chip_info = {
+ .ops = &i915_hwmon_ops,
+ .info = i915_info,
+};
+
+static void
+i915_hwmon_get_preregistration_info(struct drm_i915_private *i915)
+{
+ struct i915_hwmon *hwmon = &i915->hwmon;
+ struct intel_uncore *uncore = &i915->uncore;
+ intel_wakeref_t wakeref;
+ u32 val_sku_unit;
+ __le32 le_sku_unit;
+
+ if (IS_DG1(i915)) {
+ hwmon->rg.pkg_power_sku_unit = PCU_PACKAGE_POWER_SKU_UNIT;
+ hwmon->rg.pkg_power_sku = PCU_PACKAGE_POWER_SKU;
+ hwmon->rg.pkg_energy_status = PCU_PACKAGE_ENERGY_STATUS;
+ hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT;
+ hwmon->rg.pkg_rapl_limit_udw = PCU_PACKAGE_RAPL_LIMIT_UDW;
+ } else {
+ hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG;
+ hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
+ hwmon->rg.pkg_energy_status = INVALID_MMIO_REG;
+ hwmon->rg.pkg_rapl_limit = INVALID_MMIO_REG;
+ hwmon->rg.pkg_rapl_limit_udw = INVALID_MMIO_REG;
+ }
+
+ wakeref = intel_runtime_pm_get(uncore->rpm);
+
+ /*
+ * The contents of register hwmon->rg.pkg_power_sku_unit do not change,
+ * so read it once and store the shift values.
+ */
+ if (i915_mmio_reg_valid(hwmon->rg.pkg_power_sku_unit))
+ val_sku_unit = intel_uncore_read(uncore,
+ hwmon->rg.pkg_power_sku_unit);
+ else
+ val_sku_unit = 0;
+
+ hwmon->energy_counter_overflow = 0;
+
+ if (i915_mmio_reg_valid(hwmon->rg.pkg_energy_status))
+ hwmon->energy_counter_prev =
+ intel_uncore_read(uncore, hwmon->rg.pkg_energy_status);
+ else
+ hwmon->energy_counter_prev = 0;
+
+ intel_runtime_pm_put(uncore->rpm, wakeref);
+
+ le_sku_unit = cpu_to_le32(val_sku_unit);
+ hwmon->scl_shift_power = le32_get_bits(le_sku_unit, PKG_PWR_UNIT);
+ hwmon->scl_shift_energy = le32_get_bits(le_sku_unit, PKG_ENERGY_UNIT);
+ hwmon->scl_shift_time = le32_get_bits(le_sku_unit, PKG_TIME_UNIT);
+
+ /*
+ * There is no direct way to obtain the power default_limit.
+ * The best known workaround is to use the initial value of power1_max.
+ *
+ * The value of power1_max is reset to the default on reboot, but is
+ * not reset by a module unload/load sequence. To allow proper
+ * functioning after a module reload, the value for power1_max is
+ * restored to its original value at module unload time in
+ * i915_hwmon_unregister().
+ */
+ hwmon->power_max_initial_value =
+ (u32)_field_read_and_scale(uncore,
+ hwmon->rg.pkg_rapl_limit,
+ PKG_PWR_LIM_1,
+ FIELD_SHIFT(PKG_PWR_LIM_1),
+ hwmon->scl_shift_power, SF_POWER);
+}
+
+void i915_hwmon_register(struct drm_i915_private *i915)
+{
+ struct drm_device *drm_dev = &i915->drm;
+ struct i915_hwmon *hwmon = &i915->hwmon;
+ struct device *hwmon_dev;
+
+ mutex_init(&hwmon->hwmon_lock);
+
+ i915_hwmon_get_preregistration_info(i915);
+
+ hwmon_dev = hwmon_device_register_with_info(drm_dev->dev, "i915",
+ drm_dev,
+ &i915_chip_info,
+ hwmon_groups);
+
+ if (IS_ERR(hwmon_dev)) {
+ mutex_destroy(&hwmon->hwmon_lock);
+ drm_info(&i915->drm, "Failed to register hwmon for i915\n");
+ return;
+ }
+
+ hwmon->dev = hwmon_dev;
+}
+
+void i915_hwmon_unregister(struct drm_i915_private *i915)
+{
+ struct i915_hwmon *hwmon = &i915->hwmon;
+
+ if (hwmon->power_max_initial_value) {
+ /* Restore power1_max. */
+ _field_scale_and_write(&i915->uncore, hwmon->rg.pkg_rapl_limit,
+ PKG_PWR_LIM_1,
+ FIELD_SHIFT(PKG_PWR_LIM_1),
+ hwmon->scl_shift_power,
+ SF_POWER,
+ hwmon->power_max_initial_value);
+ }
+
+ if (hwmon->dev)
+ hwmon_device_unregister(hwmon->dev);
+
+ mutex_destroy(&hwmon->hwmon_lock);
+
+ memset(hwmon, 0, sizeof(*hwmon));
+}
diff --git a/drivers/gpu/drm/i915/i915_hwmon.h b/drivers/gpu/drm/i915/i915_hwmon.h
new file mode 100644
index 0000000000000..2fff4f9a6303f
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_hwmon.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: MIT */
+
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef __INTEL_HWMON_H__
+#define __INTEL_HWMON_H__
+
+#include <linux/types.h>
+#include <linux/mutex.h>
+#include "i915_reg.h"
+
+struct i915_hwmon_reg {
+ i915_reg_t pkg_power_sku_unit;
+ i915_reg_t pkg_power_sku;
+ i915_reg_t pkg_energy_status;
+ i915_reg_t pkg_rapl_limit;
+ i915_reg_t pkg_rapl_limit_udw;
+};
+
+struct i915_hwmon {
+ struct device *dev;
+ struct mutex hwmon_lock; /* counter overflow logic and rmw */
+
+ struct i915_hwmon_reg rg;
+
+ u32 energy_counter_overflow;
+ u32 energy_counter_prev;
+ u32 power_max_initial_value;
+
+ int scl_shift_power;
+ int scl_shift_energy;
+ int scl_shift_time;
+};
+
+struct drm_i915_private;
+
+void i915_hwmon_register(struct drm_i915_private *i915);
+void i915_hwmon_unregister(struct drm_i915_private *i915);
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4979b4965a828..931fdd3a681ac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4083,6 +4083,58 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define BXT_RP_STATE_CAP _MMIO(0x138170)
#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
+/* DG1 */
+
+/* based on MCHBAR_MIRROR_BASE_SNB == 0x140000 */
+#define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938)
+#define PCU_PACKAGE_ENERGY_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x593c)
+#define PCU_PACKAGE_RAPL_LIMIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
+#define PCU_PACKAGE_RAPL_LIMIT_UDW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a4)
+#define PCU_PACKAGE_POWER_SKU INVALID_MMIO_REG
+
+/* Fields for *_PACKAGE_RAPL_LIMIT: */
+#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
+#define PKG_PWR_LIM_1_EN REG_BIT(15)
+#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
+
+/*
+ * Fields for *_PACKAGE_RAPL_LIMIT_UDW:
+ * In docs, these fields may be defined relative to the entire 64-bit
+ * register, but here they are defined relative to the 32-bit boundary.
+ */
+#define PKG_PWR_LIM_2 REG_GENMASK(14, 0) // 46:32
+#define PKG_PWR_LIM_2_EN REG_BIT(15) // 47:47
+#define PKG_PWR_LIM_2_TIME REG_GENMASK(23, 17) // 55:49
+
+/*
+ * *_PACKAGE_POWER_SKU_UNIT - fields specifying scaling for PCU quantities.
+ * - PKG_PWR_UNIT - Power Units used for power control registers. The
+ * actual unit value is calculated by 1 W / Power(2,PKG_PWR_UNIT).
+ * - PKG_ENERGY_UNIT - Energy Units used for power control registers. The
+ * actual unit value is calculated by 1 J / Power(2,PKG_ENERGY_UNIT).
+ * - PKG_TIME_UNIT - Time Units used for power control registers. The
+ * actual unit value is calculated by 1 s / Power(2,PKG_TIME_UNIT).
+ */
+#define PKG_PWR_UNIT REG_GENMASK(3, 0)
+#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
+#define PKG_TIME_UNIT REG_GENMASK(19, 16)
+
+/*
+ * *_PACKAGE_POWER_SKU - SKU power and timing parameters.
+ * Used herein as a 64-bit bit register.
+ * These masks are defined using GENMASK_ULL as REG_GENMASK is limited to u32
+ * and as GENMASK is "long" and therefore 32-bits on a 32-bit system.
+ * PKG_PKG_TDP, PKG_MIN_PWR, and PKG_MAX_PWR are scaled in the same way as
+ * PKG_PWR_LIM_*, above.
+ * PKG_MAX_WIN has sub-fields for x and y, and has the value: is 1.x * 2^y.
+ */
+#define PKG_PKG_TDP GENMASK_ULL(14, 0)
+#define PKG_MIN_PWR GENMASK_ULL(30, 16)
+#define PKG_MAX_PWR GENMASK_ULL(46, 32)
+#define PKG_MAX_WIN GENMASK_ULL(54, 48)
+#define PKG_MAX_WIN_Y GENMASK_ULL(54, 53)
+#define PKG_MAX_WIN_X GENMASK_ULL(52, 48)
+
/*
* Logical Context regs
*/
