Thanks everybody. The initial proposal is dead. Here are some thoughts on how to do it differently.
I think we can have direct command submission from userspace via memory-mapped queues ("user queues") without changing window systems.
The memory management doesn't have to use GPU page faults like HMM. Instead, it can wait for user queues of a specific process to go idle and then unmap the queues, so that userspace can't submit anything. Buffer evictions, pinning, etc. can be executed when all queues are unmapped (suspended). Thus, no BO fences and page faults are needed.
Inter-process synchronization can use timeline semaphores. Userspace will query the wait and signal value for a shared buffer from the kernel. The kernel will keep a history of those queries to know which process is responsible for signalling which buffer. There is only the wait-timeout issue and how to identify the culprit. One of the solutions is to have the GPU send all GPU signal commands and all timed out wait commands via an interrupt to the kernel driver to monitor and validate userspace behavior. With that, it can be identified whether the culprit is the waiting process or the signalling process and which one. Invalid signal/wait parameters can also be detected. The kernel can force-signal only the semaphores that time out, and punish the processes which caused the timeout or used invalid signal/wait parameters.
The question is whether this synchronization solution is robust enough for dma_fence and whatever the kernel and window systems need.
Marek
On Tue, Apr 20, 2021 at 4:34 PM Daniel Stone <daniel@xxxxxxxxxxxxx> wrote:
_______________________________________________Hi,On Tue, 20 Apr 2021 at 20:30, Daniel Vetter <daniel@xxxxxxxx> wrote:The thing is, you can't do this in drm/scheduler. At least not without
splitting up the dma_fence in the kernel into separate memory fences
and sync fencesI'm starting to think this thread needs its own glossary ...I propose we use 'residency fence' for execution fences which enact memory-residency operations, e.g. faulting in a page ultimately depending on GPU work retiring.And 'value fence' for the pure-userspace model suggested by timeline semaphores, i.e. fences being (*addr == val) rather than being able to look at ctx seqno.Cheers,Daniel
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