still need more expert to review, so just a gentle ping for this patch
On Wed, May 27, 2020 at 4:35 PM Stephen Boyd <sboyd@xxxxxxxxxx> wrote:
>
> Quoting dillon.minfei@xxxxxxxxx (2020-05-27 00:27:29)
> > From: dillon min <dillon.minfei@xxxxxxxxx>
> >
> > This is due to misuse \u2018PLL_VCO_SAI' and'PLL_SAI' in clk-stm32f4.c
> > 'PLL_SAI' is 2, 'PLL_VCO_SAI' is 7(defined in
> > include/dt-bindings/clock/stm32fx-clock.h).
> >
> > 'post_div' point to 'post_div_data[]', 'post_div->pll_num'
> > is PLL_I2S or PLL_SAI.
> >
> > 'clks[PLL_VCO_SAI]' has valid 'struct clk_hw* ' return
> > from stm32f4_rcc_register_pll() but, at line 1777 of
> > driver/clk/clk-stm32f4.c, use the 'clks[post_div->pll_num]',
> > equal to 'clks[PLL_SAI]', this is invalid array member at that time.
> >
> > Fixes: 517633ef630e ("clk: stm32f4: Add post divisor for I2S & SAI PLLs")
> > Signed-off-by: dillon min <dillon.minfei@xxxxxxxxx>
> > ---
>
> Acked-by: Stephen Boyd <sboyd@xxxxxxxxxx>
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