> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Jani Nikula > Sent: Thursday, February 11, 2021 8:22 PM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Nikula, Jani <jani.nikula@xxxxxxxxx>; Varide, Nischal > <nischal.varide@xxxxxxxxx>; dri-devel@xxxxxxxxxxxxxxxxxxxxx > Subject: [Intel-gfx] [PATCH v3 1/9] drm/dp: add MSO related DPCD registers > > Add DPCD register definitions for eDP 1.4 Multi-SST Operation. Looks Good to me. Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx> > Cc: Nischal Varide <nischal.varide@xxxxxxxxx> > Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx > Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx> > --- > include/drm/drm_dp_helper.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index > edffd1dcca3e..632ad7faa006 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1016,6 +1016,11 @@ struct drm_device; > #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ > #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ > > +#define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4 /* eDP 1.4 */ > +# define DP_EDP_MSO_NUMBER_OF_LINKS_MASK (7 << 0) > +# define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT 0 > +# define DP_EDP_MSO_INDEPENDENT_LINK_BIT (1 << 3) > + > /* Sideband MSG Buffers */ > #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ > #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
