On 16/02/2021 22:22, Dario Binacchi wrote: > The fdd property of the tilcdc_panel_info structure must set the reqdly > bit field (bit 12 to 19) of the raster control register. The previous > statement set the least significant bit instead. > > Signed-off-by: Dario Binacchi <dariobin@xxxxxxxxx> > > --- > > drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c > index 30213708fc99..238068e28729 100644 > --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c > +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c > @@ -393,7 +393,7 @@ static void tilcdc_crtc_set_mode(struct drm_crtc *crtc) > return; > } > } > - reg |= info->fdd < 12; > + reg |= info->fdd << 12; > tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); > > if (info->invert_pxl_clk) > This is interesting, looks like this has always been broken, and in many cases sets bits 0, which is the enable bit. So we enable LCDC before even setting the fb address. How does this not blow up LCDC totally? The fix looks correct to me, but it will change the register value for boards that have apparently been working for years. Dario, did you test this on actual HW, or did you just spot the error? Reviewed-by: Tomi Valkeinen <tomi.valkeinen@xxxxxxxxxxxxxxxx> Tomi _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
