On Tue, 2021-02-16 at 20:08 +0200, Imre Deak wrote:
> Hi,
>
> thanks for respinning this patchset, some comments below.
>
> On Fri, Feb 12, 2021 at 01:50:53PM -0500, Lyude Paul wrote:
> > From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@xxxxxxxxx>
> >
> > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > setup TGP PCH.
> >
> > v2:
> > * Move Wa_14010685332 into it's own function - vsyrjala
> > * Add TODO comment about figuring out if we can move this workaround - imre
> >
> > Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@xxxxxxxxx>
> > Signed-off-by: Lyude Paul <lyude@xxxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 53 ++++++++++++++++++++++-----------
> > 1 file changed, 36 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 98145a7f28a4..7d912aa950ee 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3040,6 +3040,19 @@ static void valleyview_irq_reset(struct
> > drm_i915_private *dev_priv)
> > spin_unlock_irq(&dev_priv->irq_lock);
> > }
> >
> > +static void cnp_irq_post_reset(struct drm_i915_private *dev_priv)
>
> Maybe a better name is cnp_display_clock_wa.
>
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > +
> > + /*
> > + * Wa_14010685332:cnp/cmp,tgp,adp
>
> Bspec says this WA applies ICL onwards and it's not PCH specific, for
> instance I haven't found the GEN9/CNP/CMP WA entries for it. Please also
> add a 'clarify platforms where this applies' todo item.
>
> > + * TODO: Figure out if this workaround can be applied in the s0ix
> > suspend/resume handlers as
> > + * on earlier platforms and whether the workaround is also needed
> > for runtime suspend/resume
> > + */
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> > SBCLK_RUN_REFCLK_DIS);
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> > +}
> > +
> > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > {
> > struct intel_uncore *uncore = &dev_priv->uncore;
> > @@ -3061,8 +3074,14 @@ static void gen8_irq_reset(struct drm_i915_private
> > *dev_priv)
> > GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> >
> > - if (HAS_PCH_SPLIT(dev_priv))
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>
> It was mentioned already earlier, why is this check necessary and can't we
> just call ibx_irq_reset() for all PCHs?
>
> > + GEN3_IRQ_RESET(uncore, SDE);
> > + else if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_reset(dev_priv);
> > +
> > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > < PCH_DG1))
>
> The check could be also moved to the helper.
>
> > + cnp_irq_post_reset(dev_priv);
> > }
> >
> > static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3104,15 +3123,9 @@ static void gen11_display_irq_reset(struct
> > drm_i915_private *dev_priv)
> > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > GEN3_IRQ_RESET(uncore, SDE);
> >
> > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS,
> > SBCLK_RUN_REFCLK_DIS);
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS, 0);
> > - }
> > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > < PCH_DG1))
> > + cnp_irq_post_reset(dev_priv);
> > }
> >
> > static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3474,6 +3487,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private
> > *dev_priv)
> > ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> >
> > spt_hpd_detection_setup(dev_priv);
> > +
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > + icp_hpd_irq_setup(dev_priv);
>
> This doesn't look correct, icp_hpd_irq_setup() redoes the interrupt
> setup done already earlier in this function and
> spt_hpd_detection_setup() is probably also not correct on ICP+. Looks
> like for ICP+ we need to call icp_hpd_irq_setup() instead of
> spt_hpd_irq_setup(), but haven't checked in detail.
Could you please check :)? I don't work at Intel so you have far more access to
this information then I do.
FWIW the code -looks- mostly equivalent to me (SHOTPLUG_CTL_DDI and
SHOTPLUG_CTL_TC seem to be equivalent registers to what's set in
spt_hpd_irq_setup()), but the icelake point codepath enables an additional port,
and changes an additional register called SHPD_FILTER_CNT. I'll update it to use
this in the next patch, but please definitely confirm this. I would very much
like to avoid potentially breaking unrelated ICP systems with this.
>
> > }
> >
> > static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
> > @@ -3764,9 +3780,19 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > }
> > }
> >
> > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > + u32 mask = SDE_GMBUS_ICP;
> > +
> > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > +}
> > +
> > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > - if (HAS_PCH_SPLIT(dev_priv))
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > + icp_irq_postinstall(dev_priv);
> > + else if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_postinstall(dev_priv);
> >
> > gen8_gt_irq_postinstall(&dev_priv->gt);
> > @@ -3775,13 +3801,6 @@ static void gen8_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > gen8_master_intr_enable(dev_priv->uncore.regs);
> > }
> >
> > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > -{
> > - struct intel_uncore *uncore = &dev_priv->uncore;
> > - u32 mask = SDE_GMBUS_ICP;
> > -
> > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > -}
> >
> > static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > --
> > 2.29.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
--
Sincerely,
Lyude Paul (she/her)
Software Engineer at Red Hat
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
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