Re: [PATCH 3/3] drm/amdgpu: share scheduler score on VCN3 instances

["Deucher, Alexander" <Alexander.Deucher@xxxxxxx>]

[AMD Official Use Only - Internal Distribution Only]

I think the virt team probably wants it in amd-staging-drm-next so they can start testing it.  5.12 is getting pretty tight.  I'm not sure if there will be another drm-misc PR or not for 5.12.  Rebasing amd-staging-drm-next is turning into a challenge.  there are always a lot of regressions.  I guess that is an argument to rebase more often so we get better internal testing of it.

Alex

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From: Koenig, Christian <Christian.Koenig@xxxxxxx>
Sent: Friday, February 5, 2021 9:53 AM
To: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Liu, Leo <Leo.Liu@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>; dri-devel@xxxxxxxxxxxxxxxxxxxxx <dri-devel@xxxxxxxxxxxxxxxxxxxxx>
Subject: Re: [PATCH 3/3] drm/amdgpu: share scheduler score on VCN3 instances

 

The alternative is to wait till drm-misc-next is merged into drm-next, then rebase amd-staging-drm-next on top of that (or directly drm-misc-next) and push then.

Would give us at least a clean history. Question is rather if we want it in 5.12?

Christian.

Am 05.02.21 um 15:50 schrieb Deucher, Alexander:

[AMD Official Use Only - Internal Distribution Only]

Good question.  I think push it to drm-misc-next for upstream.  We can carry it internally in amd-staging-drm-next for internal testing and I can coordinate with drm-next.  I think the amdgpu changes are pretty straightforward, so shouldn't be too hard keep the merge straight.  I dunno. 

Alex

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From: Christian König <ckoenig.leichtzumerken@xxxxxxxxx>
Sent: Friday, February 5, 2021 4:58 AM
To: Liu, Leo <Leo.Liu@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>; dri-devel@xxxxxxxxxxxxxxxxxxxxx <dri-devel@xxxxxxxxxxxxxxxxxxxxx>; Deucher, Alexander <Alexander.Deucher@xxxxxxx>
Subject: Re: [PATCH 3/3] drm/amdgpu: share scheduler score on VCN3 instances

 

Alex how do we want to merge this?

I've just pushed the first patch to drm-misc-next since that needed a
rebase because it touches other drivers as well.

But the rest is really AMD specific and I'm not sure if the dependent
stuff is already in there as well.

So if I push it to drm-misc-next you will probably need to merge and if
I push it to amd-staging-drm-next somebody else might need to merge when
drm-misc-next is merged.

Ideas?

Christian.

Am 04.02.21 um 19:34 schrieb Leo Liu:
> The series are:
>
> Reviewed-and-Tested-by: Leo Liu <leo.liu@xxxxxxx>
>
>
> On 2021-02-04 9:44 a.m., Christian König wrote:
>> The VCN3 instances can do both decode as well as encode.
>>
>> Share the scheduler load balancing score and remove fixing encode to
>> only the second instance.
>>
>> Signed-off-by: Christian König <christian.koenig@xxxxxxx>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  1 +
>>   drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c   | 11 +++++++----
>>   2 files changed, 8 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> index 13aa417f6be7..d10bc4f0a05f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> @@ -211,6 +211,7 @@ struct amdgpu_vcn_inst {
>>       void            *saved_bo;
>>       struct amdgpu_ring    ring_dec;
>>       struct amdgpu_ring    ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
>> +    atomic_t        sched_score;
>>       struct amdgpu_irq_src    irq;
>>       struct amdgpu_vcn_reg    external;
>>       struct amdgpu_bo    *dpg_sram_bo;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> index 239a4eb52c61..b33f513fd2ac 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> @@ -171,6 +171,7 @@ static int vcn_v3_0_sw_init(void *handle)
>>         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>>           volatile struct amdgpu_fw_shared *fw_shared;
>> +
>>           if (adev->vcn.harvest_config & (1 << i))
>>               continue;
>>   @@ -198,6 +199,8 @@ static int vcn_v3_0_sw_init(void *handle)
>>           if (r)
>>               return r;
>>   +        atomic_set(&adev->vcn.inst[i].sched_score, 0);
>> +
>>           ring = &adev->vcn.inst[i].ring_dec;
>>           ring->use_doorbell = true;
>>           if (amdgpu_sriov_vf(adev)) {
>> @@ -209,7 +212,8 @@ static int vcn_v3_0_sw_init(void *handle)
>>               ring->no_scheduler = true;
>>           sprintf(ring->name, "vcn_dec_%d", i);
>>           r = amdgpu_ring_init(adev, ring, 512,
>> &adev->vcn.inst[i].irq, 0,
>> -                     AMDGPU_RING_PRIO_DEFAULT, NULL);
>> +                     AMDGPU_RING_PRIO_DEFAULT,
>> +                     &adev->vcn.inst[i].sched_score);
>>           if (r)
>>               return r;
>>   @@ -227,11 +231,10 @@ static int vcn_v3_0_sw_init(void *handle)
>>               } else {
>>                   ring->doorbell_index =
>> (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i;
>>               }
>> -            if (adev->asic_type == CHIP_SIENNA_CICHLID && i != 1)
>> -                ring->no_scheduler = true;
>>               sprintf(ring->name, "vcn_enc_%d.%d", i, j);
>>               r = amdgpu_ring_init(adev, ring, 512,
>> &adev->vcn.inst[i].irq, 0,
>> -                         AMDGPU_RING_PRIO_DEFAULT, NULL);
>> +                         AMDGPU_RING_PRIO_DEFAULT,
>> + &adev->vcn.inst[i].sched_score);
>>               if (r)
>>                   return r;
>>           }

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