Moorestown is an outdated mobile platform with apparently no users
left. Remove it from gma500. The MID chip-setup code in mid_bios.c
is now unused, so remove it as well.
Signed-off-by: Thomas Zimmermann <tzimmermann@xxxxxxx>
---
drivers/gpu/drm/gma500/Kconfig | 7 -
drivers/gpu/drm/gma500/Makefile | 10 +-
drivers/gpu/drm/gma500/framebuffer.c | 2 +-
drivers/gpu/drm/gma500/intel_gmbus.c | 5 +-
drivers/gpu/drm/gma500/mid_bios.c | 333 --------
drivers/gpu/drm/gma500/mid_bios.h | 10 -
drivers/gpu/drm/gma500/oaktrail.h | 247 ------
drivers/gpu/drm/gma500/oaktrail_crtc.c | 663 ----------------
drivers/gpu/drm/gma500/oaktrail_device.c | 567 --------------
drivers/gpu/drm/gma500/oaktrail_hdmi.c | 840 ---------------------
drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c | 331 --------
drivers/gpu/drm/gma500/oaktrail_lvds.c | 423 -----------
drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c | 169 -----
drivers/gpu/drm/gma500/psb_drv.c | 66 +-
drivers/gpu/drm/gma500/psb_drv.h | 42 --
drivers/gpu/drm/gma500/psb_intel_drv.h | 6 -
drivers/gpu/drm/gma500/psb_intel_lvds.c | 14 +-
drivers/gpu/drm/gma500/psb_intel_reg.h | 16 -
drivers/gpu/drm/gma500/psb_intel_sdvo.c | 20 +-
19 files changed, 13 insertions(+), 3758 deletions(-)
delete mode 100644 drivers/gpu/drm/gma500/mid_bios.c
delete mode 100644 drivers/gpu/drm/gma500/mid_bios.h
delete mode 100644 drivers/gpu/drm/gma500/oaktrail.h
delete mode 100644 drivers/gpu/drm/gma500/oaktrail_crtc.c
delete mode 100644 drivers/gpu/drm/gma500/oaktrail_device.c
delete mode 100644 drivers/gpu/drm/gma500/oaktrail_hdmi.c
delete mode 100644 drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c
delete mode 100644 drivers/gpu/drm/gma500/oaktrail_lvds.c
delete mode 100644 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c
diff --git a/drivers/gpu/drm/gma500/Kconfig b/drivers/gpu/drm/gma500/Kconfig
index b05116f15d97..6f41b88cf076 100644
--- a/drivers/gpu/drm/gma500/Kconfig
+++ b/drivers/gpu/drm/gma500/Kconfig
@@ -13,13 +13,6 @@ config DRM_GMA500
Intel GMA500 ('Poulsbo') and other Intel IMG based graphics
devices.
-config DRM_GMA600
- bool "Intel GMA600 support (Experimental)"
- depends on DRM_GMA500
- help
- Say yes to include support for GMA600 (Intel Moorestown/Oaktrail)
- platforms with LVDS ports. MIPI is not currently supported.
-
config DRM_GMA3600
bool "Intel GMA3600/3650 support (Experimental)"
depends on DRM_GMA500
diff --git a/drivers/gpu/drm/gma500/Makefile b/drivers/gpu/drm/gma500/Makefile
index f7dded3784fb..b33dfef17849 100644
--- a/drivers/gpu/drm/gma500/Makefile
+++ b/drivers/gpu/drm/gma500/Makefile
@@ -24,8 +24,7 @@ gma500_gfx-y += \
psb_intel_sdvo.o \
psb_lid.o \
psb_irq.o \
- psb_device.o \
- mid_bios.o
+ psb_device.o
gma500_gfx-$(CONFIG_ACPI) += opregion.o \
@@ -36,11 +35,4 @@ gma500_gfx-$(CONFIG_DRM_GMA3600) += cdv_device.o \
cdv_intel_lvds.o \
cdv_intel_dp.o
-gma500_gfx-$(CONFIG_DRM_GMA600) += oaktrail_device.o \
- oaktrail_crtc.o \
- oaktrail_lvds.o \
- oaktrail_lvds_i2c.o \
- oaktrail_hdmi.o \
- oaktrail_hdmi_i2c.o
-
obj-$(CONFIG_DRM_GMA500) += gma500_gfx.o
diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c
index ebe9dccf2d83..4dce8d49f611 100644
--- a/drivers/gpu/drm/gma500/framebuffer.c
+++ b/drivers/gpu/drm/gma500/framebuffer.c
@@ -544,7 +544,7 @@ void psb_modeset_init(struct drm_device *dev)
/* Oaktrail and Poulsbo should use BAR 2*/
pci_read_config_dword(pdev, PSB_BSM, (u32 *)&(dev->mode_config.fb_base));
- /* num pipes is 2 for PSB but 1 for Mrst */
+ /* num pipes is 2 for PSB */
for (i = 0; i < dev_priv->num_pipe; i++)
psb_intel_crtc_init(dev, i, mode_dev);
diff --git a/drivers/gpu/drm/gma500/intel_gmbus.c b/drivers/gpu/drm/gma500/intel_gmbus.c
index 370bd6451bd9..118e0f6bae6a 100644
--- a/drivers/gpu/drm/gma500/intel_gmbus.c
+++ b/drivers/gpu/drm/gma500/intel_gmbus.c
@@ -402,10 +402,7 @@ int gma_intel_setup_gmbus(struct drm_device *dev)
if (dev_priv->gmbus == NULL)
return -ENOMEM;
- if (IS_MRST(dev))
- dev_priv->gmbus_reg = dev_priv->aux_reg;
- else
- dev_priv->gmbus_reg = dev_priv->vdc_reg;
+ dev_priv->gmbus_reg = dev_priv->vdc_reg;
for (i = 0; i < GMBUS_NUM_PORTS; i++) {
struct intel_gmbus *bus = &dev_priv->gmbus[i];
diff --git a/drivers/gpu/drm/gma500/mid_bios.c b/drivers/gpu/drm/gma500/mid_bios.c
deleted file mode 100644
index 68e787924ed0..000000000000
--- a/drivers/gpu/drm/gma500/mid_bios.c
+++ /dev/null
@@ -1,333 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/**************************************************************************
- * Copyright (c) 2011, Intel Corporation.
- * All Rights Reserved.
- *
- **************************************************************************/
-
-/* TODO
- * - Split functions by vbt type
- * - Make them all take drm_device
- * - Check ioremap failures
- */
-
-#include <drm/drm.h>
-
-#include "mid_bios.h"
-#include "psb_drv.h"
-
-static void mid_get_fuse_settings(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct pci_dev *pdev = to_pci_dev(dev->dev);
- struct pci_dev *pci_root =
- pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
- 0, 0);
- uint32_t fuse_value = 0;
- uint32_t fuse_value_tmp = 0;
-
-#define FB_REG06 0xD0810600
-#define FB_MIPI_DISABLE (1 << 11)
-#define FB_REG09 0xD0810900
-#define FB_SKU_MASK 0x7000
-#define FB_SKU_SHIFT 12
-#define FB_SKU_100 0
-#define FB_SKU_100L 1
-#define FB_SKU_83 2
- if (pci_root == NULL) {
- WARN_ON(1);
- return;
- }
-
-
- pci_write_config_dword(pci_root, 0xD0, FB_REG06);
- pci_read_config_dword(pci_root, 0xD4, &fuse_value);
-
- /* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */
- if (IS_MRST(dev))
- dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
-
- DRM_INFO("internal display is %s\n",
- dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
-
- /* Prevent runtime suspend at start*/
- if (dev_priv->iLVDS_enable) {
- dev_priv->is_lvds_on = true;
- dev_priv->is_mipi_on = false;
- } else {
- dev_priv->is_mipi_on = true;
- dev_priv->is_lvds_on = false;
- }
-
- dev_priv->video_device_fuse = fuse_value;
-
- pci_write_config_dword(pci_root, 0xD0, FB_REG09);
- pci_read_config_dword(pci_root, 0xD4, &fuse_value);
-
- dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value);
- fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
-
- dev_priv->fuse_reg_value = fuse_value;
-
- switch (fuse_value_tmp) {
- case FB_SKU_100:
- dev_priv->core_freq = 200;
- break;
- case FB_SKU_100L:
- dev_priv->core_freq = 100;
- break;
- case FB_SKU_83:
- dev_priv->core_freq = 166;
- break;
- default:
- dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
- fuse_value_tmp);
- dev_priv->core_freq = 0;
- }
- dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);
- pci_dev_put(pci_root);
-}
-
-/*
- * Get the revison ID, B0:D2:F0;0x08
- */
-static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
-{
- uint32_t platform_rev_id = 0;
- struct pci_dev *pdev = to_pci_dev(dev_priv->dev->dev);
- int domain = pci_domain_nr(pdev->bus);
- struct pci_dev *pci_gfx_root =
- pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(2, 0));
-
- if (pci_gfx_root == NULL) {
- WARN_ON(1);
- return;
- }
- pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
- dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
- pci_dev_put(pci_gfx_root);
- dev_dbg(dev_priv->dev->dev, "platform_rev_id is %x\n",
- dev_priv->platform_rev_id);
-}
-
-struct mid_vbt_header {
- u32 signature;
- u8 revision;
-} __packed;
-
-/* The same for r0 and r1 */
-struct vbt_r0 {
- struct mid_vbt_header vbt_header;
- u8 size;
- u8 checksum;
-} __packed;
-
-struct vbt_r10 {
- struct mid_vbt_header vbt_header;
- u8 checksum;
- u16 size;
- u8 panel_count;
- u8 primary_panel_idx;
- u8 secondary_panel_idx;
- u8 __reserved[5];
-} __packed;
-
-static int read_vbt_r0(u32 addr, struct vbt_r0 *vbt)
-{
- void __iomem *vbt_virtual;
-
- vbt_virtual = ioremap(addr, sizeof(*vbt));
- if (vbt_virtual == NULL)
- return -1;
-
- memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
- iounmap(vbt_virtual);
-
- return 0;
-}
-
-static int read_vbt_r10(u32 addr, struct vbt_r10 *vbt)
-{
- void __iomem *vbt_virtual;
-
- vbt_virtual = ioremap(addr, sizeof(*vbt));
- if (!vbt_virtual)
- return -1;
-
- memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
- iounmap(vbt_virtual);
-
- return 0;
-}
-
-static int mid_get_vbt_data_r0(struct drm_psb_private *dev_priv, u32 addr)
-{
- struct vbt_r0 vbt;
- void __iomem *gct_virtual;
- struct gct_r0 gct;
- u8 bpi;
-
- if (read_vbt_r0(addr, &vbt))
- return -1;
-
- gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
- if (!gct_virtual)
- return -1;
- memcpy_fromio(&gct, gct_virtual, sizeof(gct));
- iounmap(gct_virtual);
-
- bpi = gct.PD.BootPanelIndex;
- dev_priv->gct_data.bpi = bpi;
- dev_priv->gct_data.pt = gct.PD.PanelType;
- dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
- dev_priv->gct_data.Panel_Port_Control =
- gct.panel[bpi].Panel_Port_Control;
- dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
- gct.panel[bpi].Panel_MIPI_Display_Descriptor;
-
- return 0;
-}
-
-static int mid_get_vbt_data_r1(struct drm_psb_private *dev_priv, u32 addr)
-{
- struct vbt_r0 vbt;
- void __iomem *gct_virtual;
- struct gct_r1 gct;
- u8 bpi;
-
- if (read_vbt_r0(addr, &vbt))
- return -1;
-
- gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
- if (!gct_virtual)
- return -1;
- memcpy_fromio(&gct, gct_virtual, sizeof(gct));
- iounmap(gct_virtual);
-
- bpi = gct.PD.BootPanelIndex;
- dev_priv->gct_data.bpi = bpi;
- dev_priv->gct_data.pt = gct.PD.PanelType;
- dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
- dev_priv->gct_data.Panel_Port_Control =
- gct.panel[bpi].Panel_Port_Control;
- dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
- gct.panel[bpi].Panel_MIPI_Display_Descriptor;
-
- return 0;
-}
-
-static int mid_get_vbt_data_r10(struct drm_psb_private *dev_priv, u32 addr)
-{
- struct vbt_r10 vbt;
- void __iomem *gct_virtual;
- struct gct_r10 *gct;
- struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD;
- struct gct_r10_timing_info *ti;
- int ret = -1;
-
- if (read_vbt_r10(addr, &vbt))
- return -1;
-
- gct = kmalloc_array(vbt.panel_count, sizeof(*gct), GFP_KERNEL);
- if (!gct)
- return -ENOMEM;
-
- gct_virtual = ioremap(addr + sizeof(vbt),
- sizeof(*gct) * vbt.panel_count);
- if (!gct_virtual)
- goto out;
- memcpy_fromio(gct, gct_virtual, sizeof(*gct));
- iounmap(gct_virtual);
-
- dev_priv->gct_data.bpi = vbt.primary_panel_idx;
- dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
- gct[vbt.primary_panel_idx].Panel_MIPI_Display_Descriptor;
-
- ti = &gct[vbt.primary_panel_idx].DTD;
- dp_ti->pixel_clock = ti->pixel_clock;
- dp_ti->hactive_hi = ti->hactive_hi;
- dp_ti->hactive_lo = ti->hactive_lo;
- dp_ti->hblank_hi = ti->hblank_hi;
- dp_ti->hblank_lo = ti->hblank_lo;
- dp_ti->hsync_offset_hi = ti->hsync_offset_hi;
- dp_ti->hsync_offset_lo = ti->hsync_offset_lo;
- dp_ti->hsync_pulse_width_hi = ti->hsync_pulse_width_hi;
- dp_ti->hsync_pulse_width_lo = ti->hsync_pulse_width_lo;
- dp_ti->vactive_hi = ti->vactive_hi;
- dp_ti->vactive_lo = ti->vactive_lo;
- dp_ti->vblank_hi = ti->vblank_hi;
- dp_ti->vblank_lo = ti->vblank_lo;
- dp_ti->vsync_offset_hi = ti->vsync_offset_hi;
- dp_ti->vsync_offset_lo = ti->vsync_offset_lo;
- dp_ti->vsync_pulse_width_hi = ti->vsync_pulse_width_hi;
- dp_ti->vsync_pulse_width_lo = ti->vsync_pulse_width_lo;
-
- ret = 0;
-out:
- kfree(gct);
- return ret;
-}
-
-static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
-{
- struct drm_device *dev = dev_priv->dev;
- struct pci_dev *pdev = to_pci_dev(dev->dev);
- u32 addr;
- u8 __iomem *vbt_virtual;
- struct mid_vbt_header vbt_header;
- struct pci_dev *pci_gfx_root =
- pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
- 0, PCI_DEVFN(2, 0));
- int ret = -1;
-
- /* Get the address of the platform config vbt */
- pci_read_config_dword(pci_gfx_root, 0xFC, &addr);
- pci_dev_put(pci_gfx_root);
-
- dev_dbg(dev->dev, "drm platform config address is %x\n", addr);
-
- if (!addr)
- goto out;
-
- /* get the virtual address of the vbt */
- vbt_virtual = ioremap(addr, sizeof(vbt_header));
- if (!vbt_virtual)
- goto out;
-
- memcpy_fromio(&vbt_header, vbt_virtual, sizeof(vbt_header));
- iounmap(vbt_virtual);
-
- if (memcmp(&vbt_header.signature, "$GCT", 4))
- goto out;
-
- dev_dbg(dev->dev, "GCT revision is %02x\n", vbt_header.revision);
-
- switch (vbt_header.revision) {
- case 0x00:
- ret = mid_get_vbt_data_r0(dev_priv, addr);
- break;
- case 0x01:
- ret = mid_get_vbt_data_r1(dev_priv, addr);
- break;
- case 0x10:
- ret = mid_get_vbt_data_r10(dev_priv, addr);
- break;
- default:
- dev_err(dev->dev, "Unknown revision of GCT!\n");
- }
-
-out:
- if (ret)
- dev_err(dev->dev, "Unable to read GCT!");
- else
- dev_priv->has_gct = true;
-}
-
-int mid_chip_setup(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- mid_get_fuse_settings(dev);
- mid_get_vbt_data(dev_priv);
- mid_get_pci_revID(dev_priv);
- return 0;
-}
diff --git a/drivers/gpu/drm/gma500/mid_bios.h b/drivers/gpu/drm/gma500/mid_bios.h
deleted file mode 100644
index 8707f7c893a7..000000000000
--- a/drivers/gpu/drm/gma500/mid_bios.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/**************************************************************************
- * Copyright (c) 2011, Intel Corporation.
- * All Rights Reserved.
- *
- **************************************************************************/
-struct drm_device;
-
-extern int mid_chip_setup(struct drm_device *dev);
-
diff --git a/drivers/gpu/drm/gma500/oaktrail.h b/drivers/gpu/drm/gma500/oaktrail.h
deleted file mode 100644
index 8d20fa2ee286..000000000000
--- a/drivers/gpu/drm/gma500/oaktrail.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/**************************************************************************
- * Copyright (c) 2007-2011, Intel Corporation.
- * All Rights Reserved.
- *
- **************************************************************************/
-
-struct psb_intel_mode_device;
-
-/* MID device specific descriptors */
-
-struct oaktrail_timing_info {
- u16 pixel_clock;
- u8 hactive_lo;
- u8 hblank_lo;
- u8 hblank_hi:4;
- u8 hactive_hi:4;
- u8 vactive_lo;
- u8 vblank_lo;
- u8 vblank_hi:4;
- u8 vactive_hi:4;
- u8 hsync_offset_lo;
- u8 hsync_pulse_width_lo;
- u8 vsync_pulse_width_lo:4;
- u8 vsync_offset_lo:4;
- u8 vsync_pulse_width_hi:2;
- u8 vsync_offset_hi:2;
- u8 hsync_pulse_width_hi:2;
- u8 hsync_offset_hi:2;
- u8 width_mm_lo;
- u8 height_mm_lo;
- u8 height_mm_hi:4;
- u8 width_mm_hi:4;
- u8 hborder;
- u8 vborder;
- u8 unknown0:1;
- u8 hsync_positive:1;
- u8 vsync_positive:1;
- u8 separate_sync:2;
- u8 stereo:1;
- u8 unknown6:1;
- u8 interlaced:1;
-} __packed;
-
-struct gct_r10_timing_info {
- u16 pixel_clock;
- u32 hactive_lo:8;
- u32 hactive_hi:4;
- u32 hblank_lo:8;
- u32 hblank_hi:4;
- u32 hsync_offset_lo:8;
- u16 hsync_offset_hi:2;
- u16 hsync_pulse_width_lo:8;
- u16 hsync_pulse_width_hi:2;
- u16 hsync_positive:1;
- u16 rsvd_1:3;
- u8 vactive_lo:8;
- u16 vactive_hi:4;
- u16 vblank_lo:8;
- u16 vblank_hi:4;
- u16 vsync_offset_lo:4;
- u16 vsync_offset_hi:2;
- u16 vsync_pulse_width_lo:4;
- u16 vsync_pulse_width_hi:2;
- u16 vsync_positive:1;
- u16 rsvd_2:3;
-} __packed;
-
-struct oaktrail_panel_descriptor_v1 {
- u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
- /* 0x61190 if MIPI */
- u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
- u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
- u32 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 dword */
- /* Register 0x61210 */
- struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
- u16 Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */
- /* Bit 0, Frequency, 15 bits,0 - 32767Hz */
- /* Bit 15, Polarity, 1 bit, 0: Normal, 1: Inverted */
- u16 Panel_MIPI_Display_Descriptor;
- /*16 bits, Defined as follows: */
- /* if MIPI, 0x0000 if LVDS */
- /* Bit 0, Type, 2 bits, */
- /* 0: Type-1, */
- /* 1: Type-2, */
- /* 2: Type-3, */
- /* 3: Type-4 */
- /* Bit 2, Pixel Format, 4 bits */
- /* Bit0: 16bpp (not supported in LNC), */
- /* Bit1: 18bpp loosely packed, */
- /* Bit2: 18bpp packed, */
- /* Bit3: 24bpp */
- /* Bit 6, Reserved, 2 bits, 00b */
- /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
- /* Bit 14, Reserved, 2 bits, 00b */
-} __packed;
-
-struct oaktrail_panel_descriptor_v2 {
- u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
- /* 0x61190 if MIPI */
- u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
- u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
- u8 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 byte */
- /* Register 0x61210 */
- struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
- u16 Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/
- /*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/
- u8 Panel_Initial_Brightness;/* [7:0] 0 - 100% */
- /*Bit 7, Polarity, 1 bit,0: Normal, 1: Inverted*/
- u16 Panel_MIPI_Display_Descriptor;
- /*16 bits, Defined as follows: */
- /* if MIPI, 0x0000 if LVDS */
- /* Bit 0, Type, 2 bits, */
- /* 0: Type-1, */
- /* 1: Type-2, */
- /* 2: Type-3, */
- /* 3: Type-4 */
- /* Bit 2, Pixel Format, 4 bits */
- /* Bit0: 16bpp (not supported in LNC), */
- /* Bit1: 18bpp loosely packed, */
- /* Bit2: 18bpp packed, */
- /* Bit3: 24bpp */
- /* Bit 6, Reserved, 2 bits, 00b */
- /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
- /* Bit 14, Reserved, 2 bits, 00b */
-} __packed;
-
-union oaktrail_panel_rx {
- struct {
- u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/
- /* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */
- u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */
- /*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/
- u16 SupportedVideoTransferMode:2; /*0: Non-burst only */
- /* 1: Burst and non-burst */
- /* 2/3: Reserved */
- u16 HSClkBehavior:1; /*0: Continuous, 1: Non-continuous*/
- u16 DuoDisplaySupport:1; /*1 bit,0: No, 1: Yes*/
- u16 ECC_ChecksumCapabilities:1;/*1 bit,0: No, 1: Yes*/
- u16 BidirectionalCommunication:1;/*1 bit,0: No, 1: Yes */
- u16 Rsvd:5;/*5 bits,00000b */
- } panelrx;
- u16 panel_receiver;
-} __packed;
-
-struct gct_r0 {
- union { /*8 bits,Defined as follows: */
- struct {
- u8 PanelType:4; /*4 bits, Bit field for panels*/
- /* 0 - 3: 0 = LVDS, 1 = MIPI*/
- /*2 bits,Specifies which of the*/
- u8 BootPanelIndex:2;
- /* 4 panels to use by default*/
- u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
- /* the 4 MIPI DSI receivers to use*/
- } PD;
- u8 PanelDescriptor;
- };
- struct oaktrail_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/
- union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
-} __packed;
-
-struct gct_r1 {
- union { /*8 bits,Defined as follows: */
- struct {
- u8 PanelType:4; /*4 bits, Bit field for panels*/
- /* 0 - 3: 0 = LVDS, 1 = MIPI*/
- /*2 bits,Specifies which of the*/
- u8 BootPanelIndex:2;
- /* 4 panels to use by default*/
- u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
- /* the 4 MIPI DSI receivers to use*/
- } PD;
- u8 PanelDescriptor;
- };
- struct oaktrail_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/
- union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
-} __packed;
-
-struct gct_r10 {
- struct gct_r10_timing_info DTD;
- u16 Panel_MIPI_Display_Descriptor;
- u16 Panel_MIPI_Receiver_Descriptor;
- u16 Panel_Backlight_Inverter_Descriptor;
- u8 Panel_Initial_Brightness;
- u32 MIPI_Ctlr_Init_ptr;
- u32 MIPI_Panel_Init_ptr;
-} __packed;
-
-struct oaktrail_gct_data {
- u8 bpi; /* boot panel index, number of panel used during boot */
- u8 pt; /* panel type, 4 bit field, 0=lvds, 1=mipi */
- struct oaktrail_timing_info DTD; /* timing info for the selected panel */
- u32 Panel_Port_Control;
- u32 PP_On_Sequencing;/*1 dword,Register 0x61208,*/
- u32 PP_Off_Sequencing;/*1 dword,Register 0x6120C,*/
- u32 PP_Cycle_Delay;
- u16 Panel_Backlight_Inverter_Descriptor;
- u16 Panel_MIPI_Display_Descriptor;
-} __packed;
-
-#define MODE_SETTING_IN_CRTC 0x1
-#define MODE_SETTING_IN_ENCODER 0x2
-#define MODE_SETTING_ON_GOING 0x3
-#define MODE_SETTING_IN_DSR 0x4
-#define MODE_SETTING_ENCODER_DONE 0x8
-
-/*
- * Moorestown HDMI interfaces
- */
-
-struct oaktrail_hdmi_dev {
- struct pci_dev *dev;
- void __iomem *regs;
- unsigned int mmio, mmio_len;
- int dpms_mode;
- struct hdmi_i2c_dev *i2c_dev;
-
- /* register state */
- u32 saveDPLL_CTRL;
- u32 saveDPLL_DIV_CTRL;
- u32 saveDPLL_ADJUST;
- u32 saveDPLL_UPDATE;
- u32 saveDPLL_CLK_ENABLE;
- u32 savePCH_HTOTAL_B;
- u32 savePCH_HBLANK_B;
- u32 savePCH_HSYNC_B;
- u32 savePCH_VTOTAL_B;
- u32 savePCH_VBLANK_B;
- u32 savePCH_VSYNC_B;
- u32 savePCH_PIPEBCONF;
- u32 savePCH_PIPEBSRC;
-};
-
-extern void oaktrail_hdmi_setup(struct drm_device *dev);
-extern void oaktrail_hdmi_teardown(struct drm_device *dev);
-extern int oaktrail_hdmi_i2c_init(struct pci_dev *dev);
-extern void oaktrail_hdmi_i2c_exit(struct pci_dev *dev);
-extern void oaktrail_hdmi_save(struct drm_device *dev);
-extern void oaktrail_hdmi_restore(struct drm_device *dev);
-extern void oaktrail_hdmi_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev);
-extern int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode, int x, int y,
- struct drm_framebuffer *old_fb);
-extern void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode);
-
-
diff --git a/drivers/gpu/drm/gma500/oaktrail_crtc.c b/drivers/gpu/drm/gma500/oaktrail_crtc.c
deleted file mode 100644
index 129f87971002..000000000000
--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
+++ /dev/null
@@ -1,663 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright © 2009 Intel Corporation
- */
-
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/pm_runtime.h>
-
-#include <drm/drm_fourcc.h>
-
-#include "framebuffer.h"
-#include "gma_display.h"
-#include "power.h"
-#include "psb_drv.h"
-#include "psb_intel_drv.h"
-#include "psb_intel_reg.h"
-
-#define MRST_LIMIT_LVDS_100L 0
-#define MRST_LIMIT_LVDS_83 1
-#define MRST_LIMIT_LVDS_100 2
-#define MRST_LIMIT_SDVO 3
-
-#define MRST_DOT_MIN 19750
-#define MRST_DOT_MAX 120000
-#define MRST_M_MIN_100L 20
-#define MRST_M_MIN_100 10
-#define MRST_M_MIN_83 12
-#define MRST_M_MAX_100L 34
-#define MRST_M_MAX_100 17
-#define MRST_M_MAX_83 20
-#define MRST_P1_MIN 2
-#define MRST_P1_MAX_0 7
-#define MRST_P1_MAX_1 8
-
-static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit,
- struct drm_crtc *crtc, int target,
- int refclk, struct gma_clock_t *best_clock);
-
-static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit,
- struct drm_crtc *crtc, int target,
- int refclk, struct gma_clock_t *best_clock);
-
-static const struct gma_limit_t mrst_limits[] = {
- { /* MRST_LIMIT_LVDS_100L */
- .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
- .m = {.min = MRST_M_MIN_100L, .max = MRST_M_MAX_100L},
- .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
- .find_pll = mrst_lvds_find_best_pll,
- },
- { /* MRST_LIMIT_LVDS_83L */
- .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
- .m = {.min = MRST_M_MIN_83, .max = MRST_M_MAX_83},
- .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_0},
- .find_pll = mrst_lvds_find_best_pll,
- },
- { /* MRST_LIMIT_LVDS_100 */
- .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
- .m = {.min = MRST_M_MIN_100, .max = MRST_M_MAX_100},
- .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
- .find_pll = mrst_lvds_find_best_pll,
- },
- { /* MRST_LIMIT_SDVO */
- .vco = {.min = 1400000, .max = 2800000},
- .n = {.min = 3, .max = 7},
- .m = {.min = 80, .max = 137},
- .p1 = {.min = 1, .max = 2},
- .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 10},
- .find_pll = mrst_sdvo_find_best_pll,
- },
-};
-
-#define MRST_M_MIN 10
-static const u32 oaktrail_m_converts[] = {
- 0x2B, 0x15, 0x2A, 0x35, 0x1A, 0x0D, 0x26, 0x33, 0x19, 0x2C,
- 0x36, 0x3B, 0x1D, 0x2E, 0x37, 0x1B, 0x2D, 0x16, 0x0B, 0x25,
- 0x12, 0x09, 0x24, 0x32, 0x39, 0x1c,
-};
-
-static const struct gma_limit_t *mrst_limit(struct drm_crtc *crtc,
- int refclk)
-{
- const struct gma_limit_t *limit = NULL;
- struct drm_device *dev = crtc->dev;
- struct drm_psb_private *dev_priv = dev->dev_private;
-
- if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
- || gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) {
- switch (dev_priv->core_freq) {
- case 100:
- limit = &mrst_limits[MRST_LIMIT_LVDS_100L];
- break;
- case 166:
- limit = &mrst_limits[MRST_LIMIT_LVDS_83];
- break;
- case 200:
- limit = &mrst_limits[MRST_LIMIT_LVDS_100];
- break;
- }
- } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
- limit = &mrst_limits[MRST_LIMIT_SDVO];
- } else {
- limit = NULL;
- dev_err(dev->dev, "mrst_limit Wrong display type.\n");
- }
-
- return limit;
-}
-
-/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
-static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock)
-{
- clock->dot = (refclk * clock->m) / (14 * clock->p1);
-}
-
-static void mrst_print_pll(struct gma_clock_t *clock)
-{
- DRM_DEBUG_DRIVER("dotclock=%d, m=%d, m1=%d, m2=%d, n=%d, p1=%d, p2=%d\n",
- clock->dot, clock->m, clock->m1, clock->m2, clock->n,
- clock->p1, clock->p2);
-}
-
-static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit,
- struct drm_crtc *crtc, int target,
- int refclk, struct gma_clock_t *best_clock)
-{
- struct gma_clock_t clock;
- u32 target_vco, actual_freq;
- s32 freq_error, min_error = 100000;
-
- memset(best_clock, 0, sizeof(*best_clock));
- memset(&clock, 0, sizeof(clock));
-
- for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
- for (clock.n = limit->n.min; clock.n <= limit->n.max;
- clock.n++) {
- for (clock.p1 = limit->p1.min;
- clock.p1 <= limit->p1.max; clock.p1++) {
- /* p2 value always stored in p2_slow on SDVO */
- clock.p = clock.p1 * limit->p2.p2_slow;
- target_vco = target * clock.p;
-
- /* VCO will increase at this point so break */
- if (target_vco > limit->vco.max)
- break;
-
- if (target_vco < limit->vco.min)
- continue;
-
- actual_freq = (refclk * clock.m) /
- (clock.n * clock.p);
- freq_error = 10000 -
- ((target * 10000) / actual_freq);
-
- if (freq_error < -min_error) {
- /* freq_error will start to decrease at
- this point so break */
- break;
- }
-
- if (freq_error < 0)
- freq_error = -freq_error;
-
- if (freq_error < min_error) {
- min_error = freq_error;
- *best_clock = clock;
- }
- }
- }
- if (min_error == 0)
- break;
- }
-
- return min_error == 0;
-}
-
-/*
- * Returns a set of divisors for the desired target clock with the given refclk,
- * or FALSE. Divisor values are the actual divisors for
- */
-static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit,
- struct drm_crtc *crtc, int target,
- int refclk, struct gma_clock_t *best_clock)
-{
- struct gma_clock_t clock;
- int err = target;
-
- memset(best_clock, 0, sizeof(*best_clock));
- memset(&clock, 0, sizeof(clock));
-
- for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
- for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max;
- clock.p1++) {
- int this_err;
-
- mrst_lvds_clock(refclk, &clock);
-
- this_err = abs(clock.dot - target);
- if (this_err < err) {
- *best_clock = clock;
- err = this_err;
- }
- }
- }
- return err != target;
-}
-
-/*
- * Sets the power management mode of the pipe and plane.
- *
- * This code should probably grow support for turning the cursor off and back
- * on appropriately at the same time as we're turning the pipe off/on.
- */
-static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode)
-{
- struct drm_device *dev = crtc->dev;
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
- int pipe = gma_crtc->pipe;
- const struct psb_offset *map = &dev_priv->regmap[pipe];
- u32 temp;
- int i;
- int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0;
-
- if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
- oaktrail_crtc_hdmi_dpms(crtc, mode);
- return;
- }
-
- if (!gma_power_begin(dev, true))
- return;
-
- /* XXX: When our outputs are all unaware of DPMS modes other than off
- * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
- */
- switch (mode) {
- case DRM_MODE_DPMS_ON:
- case DRM_MODE_DPMS_STANDBY:
- case DRM_MODE_DPMS_SUSPEND:
- for (i = 0; i <= need_aux; i++) {
- /* Enable the DPLL */
- temp = REG_READ_WITH_AUX(map->dpll, i);
- if ((temp & DPLL_VCO_ENABLE) == 0) {
- REG_WRITE_WITH_AUX(map->dpll, temp, i);
- REG_READ_WITH_AUX(map->dpll, i);
- /* Wait for the clocks to stabilize. */
- udelay(150);
- REG_WRITE_WITH_AUX(map->dpll,
- temp | DPLL_VCO_ENABLE, i);
- REG_READ_WITH_AUX(map->dpll, i);
- /* Wait for the clocks to stabilize. */
- udelay(150);
- REG_WRITE_WITH_AUX(map->dpll,
- temp | DPLL_VCO_ENABLE, i);
- REG_READ_WITH_AUX(map->dpll, i);
- /* Wait for the clocks to stabilize. */
- udelay(150);
- }
-
- /* Enable the pipe */
- temp = REG_READ_WITH_AUX(map->conf, i);
- if ((temp & PIPEACONF_ENABLE) == 0) {
- REG_WRITE_WITH_AUX(map->conf,
- temp | PIPEACONF_ENABLE, i);
- }
-
- /* Enable the plane */
- temp = REG_READ_WITH_AUX(map->cntr, i);
- if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
- REG_WRITE_WITH_AUX(map->cntr,
- temp | DISPLAY_PLANE_ENABLE,
- i);
- /* Flush the plane changes */
- REG_WRITE_WITH_AUX(map->base,
- REG_READ_WITH_AUX(map->base, i), i);
- }
-
- }
- gma_crtc_load_lut(crtc);
-
- /* Give the overlay scaler a chance to enable
- if it's on this pipe */
- /* psb_intel_crtc_dpms_video(crtc, true); TODO */
- break;
- case DRM_MODE_DPMS_OFF:
- /* Give the overlay scaler a chance to disable
- * if it's on this pipe */
- /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
-
- for (i = 0; i <= need_aux; i++) {
- /* Disable the VGA plane that we never use */
- REG_WRITE_WITH_AUX(VGACNTRL, VGA_DISP_DISABLE, i);
- /* Disable display plane */
- temp = REG_READ_WITH_AUX(map->cntr, i);
- if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
- REG_WRITE_WITH_AUX(map->cntr,
- temp & ~DISPLAY_PLANE_ENABLE, i);
- /* Flush the plane changes */
- REG_WRITE_WITH_AUX(map->base,
- REG_READ(map->base), i);
- REG_READ_WITH_AUX(map->base, i);
- }
-
- /* Next, disable display pipes */
- temp = REG_READ_WITH_AUX(map->conf, i);
- if ((temp & PIPEACONF_ENABLE) != 0) {
- REG_WRITE_WITH_AUX(map->conf,
- temp & ~PIPEACONF_ENABLE, i);
- REG_READ_WITH_AUX(map->conf, i);
- }
- /* Wait for for the pipe disable to take effect. */
- gma_wait_for_vblank(dev);
-
- temp = REG_READ_WITH_AUX(map->dpll, i);
- if ((temp & DPLL_VCO_ENABLE) != 0) {
- REG_WRITE_WITH_AUX(map->dpll,
- temp & ~DPLL_VCO_ENABLE, i);
- REG_READ_WITH_AUX(map->dpll, i);
- }
-
- /* Wait for the clocks to turn off. */
- udelay(150);
- }
- break;
- }
-
- /* Set FIFO Watermarks (values taken from EMGD) */
- REG_WRITE(DSPARB, 0x3f80);
- REG_WRITE(DSPFW1, 0x3f8f0404);
- REG_WRITE(DSPFW2, 0x04040f04);
- REG_WRITE(DSPFW3, 0x0);
- REG_WRITE(DSPFW4, 0x04040404);
- REG_WRITE(DSPFW5, 0x04040404);
- REG_WRITE(DSPFW6, 0x78);
- REG_WRITE(DSPCHICKENBIT, REG_READ(DSPCHICKENBIT) | 0xc040);
-
- gma_power_end(dev);
-}
-
-/*
- * Return the pipe currently connected to the panel fitter,
- * or -1 if the panel fitter is not present or not in use
- */
-static int oaktrail_panel_fitter_pipe(struct drm_device *dev)
-{
- u32 pfit_control;
-
- pfit_control = REG_READ(PFIT_CONTROL);
-
- /* See if the panel fitter is in use */
- if ((pfit_control & PFIT_ENABLE) == 0)
- return -1;
- return (pfit_control >> 29) & 3;
-}
-
-static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode,
- int x, int y,
- struct drm_framebuffer *old_fb)
-{
- struct drm_device *dev = crtc->dev;
- struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
- struct drm_psb_private *dev_priv = dev->dev_private;
- int pipe = gma_crtc->pipe;
- const struct psb_offset *map = &dev_priv->regmap[pipe];
- int refclk = 0;
- struct gma_clock_t clock;
- const struct gma_limit_t *limit;
- u32 dpll = 0, fp = 0, dspcntr, pipeconf;
- bool ok, is_sdvo = false;
- bool is_lvds = false;
- bool is_mipi = false;
- struct drm_mode_config *mode_config = &dev->mode_config;
- struct gma_encoder *gma_encoder = NULL;
- uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN;
- struct drm_connector *connector;
- int i;
- int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0;
-
- if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
- return oaktrail_crtc_hdmi_mode_set(crtc, mode, adjusted_mode, x, y, old_fb);
-
- if (!gma_power_begin(dev, true))
- return 0;
-
- memcpy(&gma_crtc->saved_mode,
- mode,
- sizeof(struct drm_display_mode));
- memcpy(&gma_crtc->saved_adjusted_mode,
- adjusted_mode,
- sizeof(struct drm_display_mode));
-
- list_for_each_entry(connector, &mode_config->connector_list, head) {
- if (!connector->encoder || connector->encoder->crtc != crtc)
- continue;
-
- gma_encoder = gma_attached_encoder(connector);
-
- switch (gma_encoder->type) {
- case INTEL_OUTPUT_LVDS:
- is_lvds = true;
- break;
- case INTEL_OUTPUT_SDVO:
- is_sdvo = true;
- break;
- case INTEL_OUTPUT_MIPI:
- is_mipi = true;
- break;
- }
- }
-
- /* Disable the VGA plane that we never use */
- for (i = 0; i <= need_aux; i++)
- REG_WRITE_WITH_AUX(VGACNTRL, VGA_DISP_DISABLE, i);
-
- /* Disable the panel fitter if it was on our pipe */
- if (oaktrail_panel_fitter_pipe(dev) == pipe)
- REG_WRITE(PFIT_CONTROL, 0);
-
- for (i = 0; i <= need_aux; i++) {
- REG_WRITE_WITH_AUX(map->src, ((mode->crtc_hdisplay - 1) << 16) |
- (mode->crtc_vdisplay - 1), i);
- }
-
- if (gma_encoder)
- drm_object_property_get_value(&connector->base,
- dev->mode_config.scaling_mode_property, &scalingType);
-
- if (scalingType == DRM_MODE_SCALE_NO_SCALE) {
- /* Moorestown doesn't have register support for centering so
- * we need to mess with the h/vblank and h/vsync start and
- * ends to get centering */
- int offsetX = 0, offsetY = 0;
-
- offsetX = (adjusted_mode->crtc_hdisplay -
- mode->crtc_hdisplay) / 2;
- offsetY = (adjusted_mode->crtc_vdisplay -
- mode->crtc_vdisplay) / 2;
-
- for (i = 0; i <= need_aux; i++) {
- REG_WRITE_WITH_AUX(map->htotal, (mode->crtc_hdisplay - 1) |
- ((adjusted_mode->crtc_htotal - 1) << 16), i);
- REG_WRITE_WITH_AUX(map->vtotal, (mode->crtc_vdisplay - 1) |
- ((adjusted_mode->crtc_vtotal - 1) << 16), i);
- REG_WRITE_WITH_AUX(map->hblank,
- (adjusted_mode->crtc_hblank_start - offsetX - 1) |
- ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16), i);
- REG_WRITE_WITH_AUX(map->hsync,
- (adjusted_mode->crtc_hsync_start - offsetX - 1) |
- ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16), i);
- REG_WRITE_WITH_AUX(map->vblank,
- (adjusted_mode->crtc_vblank_start - offsetY - 1) |
- ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16), i);
- REG_WRITE_WITH_AUX(map->vsync,
- (adjusted_mode->crtc_vsync_start - offsetY - 1) |
- ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16), i);
- }
- } else {
- for (i = 0; i <= need_aux; i++) {
- REG_WRITE_WITH_AUX(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
- ((adjusted_mode->crtc_htotal - 1) << 16), i);
- REG_WRITE_WITH_AUX(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
- ((adjusted_mode->crtc_vtotal - 1) << 16), i);
- REG_WRITE_WITH_AUX(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
- ((adjusted_mode->crtc_hblank_end - 1) << 16), i);
- REG_WRITE_WITH_AUX(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
- ((adjusted_mode->crtc_hsync_end - 1) << 16), i);
- REG_WRITE_WITH_AUX(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
- ((adjusted_mode->crtc_vblank_end - 1) << 16), i);
- REG_WRITE_WITH_AUX(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
- ((adjusted_mode->crtc_vsync_end - 1) << 16), i);
- }
- }
-
- /* Flush the plane changes */
- {
- const struct drm_crtc_helper_funcs *crtc_funcs =
- crtc->helper_private;
- crtc_funcs->mode_set_base(crtc, x, y, old_fb);
- }
-
- /* setup pipeconf */
- pipeconf = REG_READ(map->conf);
-
- /* Set up the display plane register */
- dspcntr = REG_READ(map->cntr);
- dspcntr |= DISPPLANE_GAMMA_ENABLE;
-
- if (pipe == 0)
- dspcntr |= DISPPLANE_SEL_PIPE_A;
- else
- dspcntr |= DISPPLANE_SEL_PIPE_B;
-
- if (is_mipi)
- goto oaktrail_crtc_mode_set_exit;
-
-
- dpll = 0; /*BIT16 = 0 for 100MHz reference */
-
- refclk = is_sdvo ? 96000 : dev_priv->core_freq * 1000;
- limit = mrst_limit(crtc, refclk);
- ok = limit->find_pll(limit, crtc, adjusted_mode->clock,
- refclk, &clock);
-
- if (is_sdvo) {
- /* Convert calculated values to register values */
- clock.p1 = (1L << (clock.p1 - 1));
- clock.m -= 2;
- clock.n = (1L << (clock.n - 1));
- }
-
- if (!ok)
- DRM_ERROR("Failed to find proper PLL settings");
-
- mrst_print_pll(&clock);
-
- if (is_sdvo)
- fp = clock.n << 16 | clock.m;
- else
- fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8;
-
- dpll |= DPLL_VGA_MODE_DIS;
-
-
- dpll |= DPLL_VCO_ENABLE;
-
- if (is_lvds)
- dpll |= DPLLA_MODE_LVDS;
- else
- dpll |= DPLLB_MODE_DAC_SERIAL;
-
- if (is_sdvo) {
- int sdvo_pixel_multiply =
- adjusted_mode->clock / mode->clock;
-
- dpll |= DPLL_DVO_HIGH_SPEED;
- dpll |=
- (sdvo_pixel_multiply -
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
- }
-
-
- /* compute bitmask from p1 value */
- if (is_sdvo)
- dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16;
- else
- dpll |= (1 << (clock.p1 - 2)) << 17;
-
- dpll |= DPLL_VCO_ENABLE;
-
- if (dpll & DPLL_VCO_ENABLE) {
- for (i = 0; i <= need_aux; i++) {
- REG_WRITE_WITH_AUX(map->fp0, fp, i);
- REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i);
- REG_READ_WITH_AUX(map->dpll, i);
- /* Check the DPLLA lock bit PIPEACONF[29] */
- udelay(150);
- }
- }
-
- for (i = 0; i <= need_aux; i++) {
- REG_WRITE_WITH_AUX(map->fp0, fp, i);
- REG_WRITE_WITH_AUX(map->dpll, dpll, i);
- REG_READ_WITH_AUX(map->dpll, i);
- /* Wait for the clocks to stabilize. */
- udelay(150);
-
- /* write it again -- the BIOS does, after all */
- REG_WRITE_WITH_AUX(map->dpll, dpll, i);
- REG_READ_WITH_AUX(map->dpll, i);
- /* Wait for the clocks to stabilize. */
- udelay(150);
-
- REG_WRITE_WITH_AUX(map->conf, pipeconf, i);
- REG_READ_WITH_AUX(map->conf, i);
- gma_wait_for_vblank(dev);
-
- REG_WRITE_WITH_AUX(map->cntr, dspcntr, i);
- gma_wait_for_vblank(dev);
- }
-
-oaktrail_crtc_mode_set_exit:
- gma_power_end(dev);
- return 0;
-}
-
-static int oaktrail_pipe_set_base(struct drm_crtc *crtc,
- int x, int y, struct drm_framebuffer *old_fb)
-{
- struct drm_device *dev = crtc->dev;
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
- struct drm_framebuffer *fb = crtc->primary->fb;
- int pipe = gma_crtc->pipe;
- const struct psb_offset *map = &dev_priv->regmap[pipe];
- unsigned long start, offset;
-
- u32 dspcntr;
- int ret = 0;
-
- /* no fb bound */
- if (!fb) {
- dev_dbg(dev->dev, "No FB bound\n");
- return 0;
- }
-
- if (!gma_power_begin(dev, true))
- return 0;
-
- start = to_gtt_range(fb->obj[0])->offset;
- offset = y * fb->pitches[0] + x * fb->format->cpp[0];
-
- REG_WRITE(map->stride, fb->pitches[0]);
-
- dspcntr = REG_READ(map->cntr);
- dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
-
- switch (fb->format->cpp[0] * 8) {
- case 8:
- dspcntr |= DISPPLANE_8BPP;
- break;
- case 16:
- if (fb->format->depth == 15)
- dspcntr |= DISPPLANE_15_16BPP;
- else
- dspcntr |= DISPPLANE_16BPP;
- break;
- case 24:
- case 32:
- dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
- break;
- default:
- dev_err(dev->dev, "Unknown color depth\n");
- ret = -EINVAL;
- goto pipe_set_base_exit;
- }
- REG_WRITE(map->cntr, dspcntr);
-
- REG_WRITE(map->base, offset);
- REG_READ(map->base);
- REG_WRITE(map->surf, start);
- REG_READ(map->surf);
-
-pipe_set_base_exit:
- gma_power_end(dev);
- return ret;
-}
-
-const struct drm_crtc_helper_funcs oaktrail_helper_funcs = {
- .dpms = oaktrail_crtc_dpms,
- .mode_set = oaktrail_crtc_mode_set,
- .mode_set_base = oaktrail_pipe_set_base,
- .prepare = gma_crtc_prepare,
- .commit = gma_crtc_commit,
-};
-
-/* Not used yet */
-const struct gma_clock_funcs mrst_clock_funcs = {
- .clock = mrst_lvds_clock,
- .limit = mrst_limit,
- .pll_is_valid = gma_pll_is_valid,
-};
diff --git a/drivers/gpu/drm/gma500/oaktrail_device.c b/drivers/gpu/drm/gma500/oaktrail_device.c
deleted file mode 100644
index 08cd5f73c868..000000000000
--- a/drivers/gpu/drm/gma500/oaktrail_device.c
+++ /dev/null
@@ -1,567 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/**************************************************************************
- * Copyright (c) 2011, Intel Corporation.
- * All Rights Reserved.
- *
- **************************************************************************/
-
-#include <linux/backlight.h>
-#include <linux/delay.h>
-#include <linux/dmi.h>
-#include <linux/module.h>
-
-#include <asm/intel-mid.h>
-#include <asm/intel_scu_ipc.h>
-
-#include <drm/drm.h>
-
-#include "intel_bios.h"
-#include "mid_bios.h"
-#include "psb_drv.h"
-#include "psb_intel_reg.h"
-#include "psb_reg.h"
-
-static int oaktrail_output_init(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- if (dev_priv->iLVDS_enable)
- oaktrail_lvds_init(dev, &dev_priv->mode_dev);
- else
- dev_err(dev->dev, "DSI is not supported\n");
- if (dev_priv->hdmi_priv)
- oaktrail_hdmi_init(dev, &dev_priv->mode_dev);
-
- psb_intel_sdvo_init(dev, SDVOB);
-
- return 0;
-}
-
-/*
- * Provide the low level interfaces for the Moorestown backlight
- */
-
-#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
-
-#define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
-#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
-#define BLC_PWM_FREQ_CALC_CONSTANT 32
-#define MHz 1000000
-#define BLC_ADJUSTMENT_MAX 100
-
-static struct backlight_device *oaktrail_backlight_device;
-static int oaktrail_brightness;
-
-static int oaktrail_set_brightness(struct backlight_device *bd)
-{
- struct drm_device *dev = bl_get_data(oaktrail_backlight_device);
- struct drm_psb_private *dev_priv = dev->dev_private;
- int level = bd->props.brightness;
- u32 blc_pwm_ctl;
- u32 max_pwm_blc;
-
- /* Percentage 1-100% being valid */
- if (level < 1)
- level = 1;
-
- if (gma_power_begin(dev, 0)) {
- /* Calculate and set the brightness value */
- max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;
- blc_pwm_ctl = level * max_pwm_blc / 100;
-
- /* Adjust the backlight level with the percent in
- * dev_priv->blc_adj1;
- */
- blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;
- blc_pwm_ctl = blc_pwm_ctl / 100;
-
- /* Adjust the backlight level with the percent in
- * dev_priv->blc_adj2;
- */
- blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2;
- blc_pwm_ctl = blc_pwm_ctl / 100;
-
- /* force PWM bit on */
- REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
- REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl);
- gma_power_end(dev);
- }
- oaktrail_brightness = level;
- return 0;
-}
-
-static int oaktrail_get_brightness(struct backlight_device *bd)
-{
- /* return locally cached var instead of HW read (due to DPST etc.) */
- /* FIXME: ideally return actual value in case firmware fiddled with
- it */
- return oaktrail_brightness;
-}
-
-static int device_backlight_init(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- unsigned long core_clock;
- u16 bl_max_freq;
- uint32_t value;
- uint32_t blc_pwm_precision_factor;
-
- dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;
- dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;
- bl_max_freq = 256;
- /* this needs to be set elsewhere */
- blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR;
-
- core_clock = dev_priv->core_freq;
-
- value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
- value *= blc_pwm_precision_factor;
- value /= bl_max_freq;
- value /= blc_pwm_precision_factor;
-
- if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ)
- return -ERANGE;
-
- if (gma_power_begin(dev, false)) {
- REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
- REG_WRITE(BLC_PWM_CTL, value | (value << 16));
- gma_power_end(dev);
- }
- return 0;
-}
-
-static const struct backlight_ops oaktrail_ops = {
- .get_brightness = oaktrail_get_brightness,
- .update_status = oaktrail_set_brightness,
-};
-
-static int oaktrail_backlight_init(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- int ret;
- struct backlight_properties props;
-
- memset(&props, 0, sizeof(struct backlight_properties));
- props.max_brightness = 100;
- props.type = BACKLIGHT_PLATFORM;
-
- oaktrail_backlight_device = backlight_device_register("oaktrail-bl",
- NULL, (void *)dev, &oaktrail_ops, &props);
-
- if (IS_ERR(oaktrail_backlight_device))
- return PTR_ERR(oaktrail_backlight_device);
-
- ret = device_backlight_init(dev);
- if (ret < 0) {
- backlight_device_unregister(oaktrail_backlight_device);
- return ret;
- }
- oaktrail_backlight_device->props.brightness = 100;
- oaktrail_backlight_device->props.max_brightness = 100;
- backlight_update_status(oaktrail_backlight_device);
- dev_priv->backlight_device = oaktrail_backlight_device;
- return 0;
-}
-
-#endif
-
-/*
- * Provide the Moorestown specific chip logic and low level methods
- * for power management
- */
-
-/**
- * oaktrail_save_display_registers - save registers lost on suspend
- * @dev: our DRM device
- *
- * Save the state we need in order to be able to restore the interface
- * upon resume from suspend
- */
-static int oaktrail_save_display_registers(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct psb_save_area *regs = &dev_priv->regs;
- struct psb_pipe *p = ®s->pipe[0];
- int i;
- u32 pp_stat;
-
- /* Display arbitration control + watermarks */
- regs->psb.saveDSPARB = PSB_RVDC32(DSPARB);
- regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1);
- regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2);
- regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3);
- regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4);
- regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5);
- regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6);
- regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
-
- /* Pipe & plane A info */
- p->conf = PSB_RVDC32(PIPEACONF);
- p->src = PSB_RVDC32(PIPEASRC);
- p->fp0 = PSB_RVDC32(MRST_FPA0);
- p->fp1 = PSB_RVDC32(MRST_FPA1);
- p->dpll = PSB_RVDC32(MRST_DPLL_A);
- p->htotal = PSB_RVDC32(HTOTAL_A);
- p->hblank = PSB_RVDC32(HBLANK_A);
- p->hsync = PSB_RVDC32(HSYNC_A);
- p->vtotal = PSB_RVDC32(VTOTAL_A);
- p->vblank = PSB_RVDC32(VBLANK_A);
- p->vsync = PSB_RVDC32(VSYNC_A);
- regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
- p->cntr = PSB_RVDC32(DSPACNTR);
- p->stride = PSB_RVDC32(DSPASTRIDE);
- p->addr = PSB_RVDC32(DSPABASE);
- p->surf = PSB_RVDC32(DSPASURF);
- p->linoff = PSB_RVDC32(DSPALINOFF);
- p->tileoff = PSB_RVDC32(DSPATILEOFF);
-
- /* Save cursor regs */
- regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
- regs->psb.saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
- regs->psb.saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);
-
- /* Save palette (gamma) */
- for (i = 0; i < 256; i++)
- p->palette[i] = PSB_RVDC32(PALETTE_A + (i << 2));
-
- if (dev_priv->hdmi_priv)
- oaktrail_hdmi_save(dev);
-
- /* Save performance state */
- regs->psb.savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);
-
- /* LVDS state */
- regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
- regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
- regs->psb.savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
- regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);
- regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
- regs->psb.saveLVDS = PSB_RVDC32(LVDS);
- regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
- regs->psb.savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
- regs->psb.savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
- regs->psb.savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);
-
- /* HW overlay */
- regs->psb.saveOV_OVADD = PSB_RVDC32(OV_OVADD);
- regs->psb.saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
- regs->psb.saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
- regs->psb.saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
- regs->psb.saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
- regs->psb.saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
- regs->psb.saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);
-
- /* DPST registers */
- regs->psb.saveHISTOGRAM_INT_CONTROL_REG =
- PSB_RVDC32(HISTOGRAM_INT_CONTROL);
- regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG =
- PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
- regs->psb.savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);
-
- if (dev_priv->iLVDS_enable) {
- /* Shut down the panel */
- PSB_WVDC32(0, PP_CONTROL);
-
- do {
- pp_stat = PSB_RVDC32(PP_STATUS);
- } while (pp_stat & 0x80000000);
-
- /* Turn off the plane */
- PSB_WVDC32(0x58000000, DSPACNTR);
- /* Trigger the plane disable */
- PSB_WVDC32(0, DSPASURF);
-
- /* Wait ~4 ticks */
- msleep(4);
-
- /* Turn off pipe */
- PSB_WVDC32(0x0, PIPEACONF);
- /* Wait ~8 ticks */
- msleep(8);
-
- /* Turn off PLLs */
- PSB_WVDC32(0, MRST_DPLL_A);
- }
- return 0;
-}
-
-/**
- * oaktrail_restore_display_registers - restore lost register state
- * @dev: our DRM device
- *
- * Restore register state that was lost during suspend and resume.
- */
-static int oaktrail_restore_display_registers(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct psb_save_area *regs = &dev_priv->regs;
- struct psb_pipe *p = ®s->pipe[0];
- u32 pp_stat;
- int i;
-
- /* Display arbitration + watermarks */
- PSB_WVDC32(regs->psb.saveDSPARB, DSPARB);
- PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1);
- PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2);
- PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3);
- PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4);
- PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5);
- PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6);
- PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT);
-
- /* Make sure VGA plane is off. it initializes to on after reset!*/
- PSB_WVDC32(0x80000000, VGACNTRL);
-
- /* set the plls */
- PSB_WVDC32(p->fp0, MRST_FPA0);
- PSB_WVDC32(p->fp1, MRST_FPA1);
-
- /* Actually enable it */
- PSB_WVDC32(p->dpll, MRST_DPLL_A);
- udelay(150);
-
- /* Restore mode */
- PSB_WVDC32(p->htotal, HTOTAL_A);
- PSB_WVDC32(p->hblank, HBLANK_A);
- PSB_WVDC32(p->hsync, HSYNC_A);
- PSB_WVDC32(p->vtotal, VTOTAL_A);
- PSB_WVDC32(p->vblank, VBLANK_A);
- PSB_WVDC32(p->vsync, VSYNC_A);
- PSB_WVDC32(p->src, PIPEASRC);
- PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A);
-
- /* Restore performance mode*/
- PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE);
-
- /* Enable the pipe*/
- if (dev_priv->iLVDS_enable)
- PSB_WVDC32(p->conf, PIPEACONF);
-
- /* Set up the plane*/
- PSB_WVDC32(p->linoff, DSPALINOFF);
- PSB_WVDC32(p->stride, DSPASTRIDE);
- PSB_WVDC32(p->tileoff, DSPATILEOFF);
-
- /* Enable the plane */
- PSB_WVDC32(p->cntr, DSPACNTR);
- PSB_WVDC32(p->surf, DSPASURF);
-
- /* Enable Cursor A */
- PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR);
- PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS);
- PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE);
-
- /* Restore palette (gamma) */
- for (i = 0; i < 256; i++)
- PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2));
-
- if (dev_priv->hdmi_priv)
- oaktrail_hdmi_restore(dev);
-
- if (dev_priv->iLVDS_enable) {
- PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
- PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/
- PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL);
- PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
- PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
- PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL);
- PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON);
- PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF);
- PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE);
- PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL);
- }
-
- /* Wait for cycle delay */
- do {
- pp_stat = PSB_RVDC32(PP_STATUS);
- } while (pp_stat & 0x08000000);
-
- /* Wait for panel power up */
- do {
- pp_stat = PSB_RVDC32(PP_STATUS);
- } while (pp_stat & 0x10000000);
-
- /* Restore HW overlay */
- PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD);
- PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0);
- PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1);
- PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2);
- PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3);
- PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4);
- PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5);
-
- /* DPST registers */
- PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG,
- HISTOGRAM_INT_CONTROL);
- PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG,
- HISTOGRAM_LOGIC_CONTROL);
- PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);
-
- return 0;
-}
-
-/**
- * oaktrail_power_down - power down the display island
- * @dev: our DRM device
- *
- * Power down the display interface of our device
- */
-static int oaktrail_power_down(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- u32 pwr_mask ;
- u32 pwr_sts;
-
- pwr_mask = PSB_PWRGT_DISPLAY_MASK;
- outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC);
-
- while (true) {
- pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
- if ((pwr_sts & pwr_mask) == pwr_mask)
- break;
- else
- udelay(10);
- }
- return 0;
-}
-
-/*
- * oaktrail_power_up
- *
- * Restore power to the specified island(s) (powergating)
- */
-static int oaktrail_power_up(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK;
- u32 pwr_sts, pwr_cnt;
-
- pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
- pwr_cnt &= ~pwr_mask;
- outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC));
-
- while (true) {
- pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
- if ((pwr_sts & pwr_mask) == 0)
- break;
- else
- udelay(10);
- }
- return 0;
-}
-
-/* Oaktrail */
-static const struct psb_offset oaktrail_regmap[2] = {
- {
- .fp0 = MRST_FPA0,
- .fp1 = MRST_FPA1,
- .cntr = DSPACNTR,
- .conf = PIPEACONF,
- .src = PIPEASRC,
- .dpll = MRST_DPLL_A,
- .htotal = HTOTAL_A,
- .hblank = HBLANK_A,
- .hsync = HSYNC_A,
- .vtotal = VTOTAL_A,
- .vblank = VBLANK_A,
- .vsync = VSYNC_A,
- .stride = DSPASTRIDE,
- .size = DSPASIZE,
- .pos = DSPAPOS,
- .surf = DSPASURF,
- .addr = MRST_DSPABASE,
- .base = MRST_DSPABASE,
- .status = PIPEASTAT,
- .linoff = DSPALINOFF,
- .tileoff = DSPATILEOFF,
- .palette = PALETTE_A,
- },
- {
- .fp0 = FPB0,
- .fp1 = FPB1,
- .cntr = DSPBCNTR,
- .conf = PIPEBCONF,
- .src = PIPEBSRC,
- .dpll = DPLL_B,
- .htotal = HTOTAL_B,
- .hblank = HBLANK_B,
- .hsync = HSYNC_B,
- .vtotal = VTOTAL_B,
- .vblank = VBLANK_B,
- .vsync = VSYNC_B,
- .stride = DSPBSTRIDE,
- .size = DSPBSIZE,
- .pos = DSPBPOS,
- .surf = DSPBSURF,
- .addr = DSPBBASE,
- .base = DSPBBASE,
- .status = PIPEBSTAT,
- .linoff = DSPBLINOFF,
- .tileoff = DSPBTILEOFF,
- .palette = PALETTE_B,
- },
-};
-
-static int oaktrail_chip_setup(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct pci_dev *pdev = to_pci_dev(dev->dev);
- int ret;
-
- if (pci_enable_msi(pdev))
- dev_warn(dev->dev, "Enabling MSI failed!\n");
-
- dev_priv->regmap = oaktrail_regmap;
-
- ret = mid_chip_setup(dev);
- if (ret < 0)
- return ret;
- if (!dev_priv->has_gct) {
- /* Now pull the BIOS data */
- psb_intel_opregion_init(dev);
- psb_intel_init_bios(dev);
- }
- gma_intel_setup_gmbus(dev);
- oaktrail_hdmi_setup(dev);
- return 0;
-}
-
-static void oaktrail_teardown(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
-
- gma_intel_teardown_gmbus(dev);
- oaktrail_hdmi_teardown(dev);
- if (!dev_priv->has_gct)
- psb_intel_destroy_bios(dev);
-}
-
-const struct psb_ops oaktrail_chip_ops = {
- .name = "Oaktrail",
- .pipes = 2,
- .crtcs = 2,
- .hdmi_mask = (1 << 1),
- .lvds_mask = (1 << 0),
- .sdvo_mask = (1 << 1),
- .cursor_needs_phys = 0,
- .sgx_offset = MRST_SGX_OFFSET,
-
- .chip_setup = oaktrail_chip_setup,
- .chip_teardown = oaktrail_teardown,
- .crtc_helper = &oaktrail_helper_funcs,
- .crtc_funcs = &psb_intel_crtc_funcs,
-
- .output_init = oaktrail_output_init,
-
-#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
- .backlight_init = oaktrail_backlight_init,
-#endif
-
- .save_regs = oaktrail_save_display_registers,
- .restore_regs = oaktrail_restore_display_registers,
- .save_crtc = gma_crtc_save,
- .restore_crtc = gma_crtc_restore,
- .power_down = oaktrail_power_down,
- .power_up = oaktrail_power_up,
-
- .i2c_bus = 1,
-};
diff --git a/drivers/gpu/drm/gma500/oaktrail_hdmi.c b/drivers/gpu/drm/gma500/oaktrail_hdmi.c
deleted file mode 100644
index a097a59a9eae..000000000000
--- a/drivers/gpu/drm/gma500/oaktrail_hdmi.c
+++ /dev/null
@@ -1,840 +0,0 @@
-/*
- * Copyright © 2010 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Li Peng <peng.li@xxxxxxxxx>
- */
-
-#include <linux/delay.h>
-
-#include <drm/drm.h>
-#include <drm/drm_simple_kms_helper.h>
-
-#include "psb_drv.h"
-#include "psb_intel_drv.h"
-#include "psb_intel_reg.h"
-
-#define HDMI_READ(reg) readl(hdmi_dev->regs + (reg))
-#define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg))
-
-#define HDMI_HCR 0x1000
-#define HCR_ENABLE_HDCP (1 << 5)
-#define HCR_ENABLE_AUDIO (1 << 2)
-#define HCR_ENABLE_PIXEL (1 << 1)
-#define HCR_ENABLE_TMDS (1 << 0)
-
-#define HDMI_HICR 0x1004
-#define HDMI_HSR 0x1008
-#define HDMI_HISR 0x100C
-#define HDMI_DETECT_HDP (1 << 0)
-
-#define HDMI_VIDEO_REG 0x3000
-#define HDMI_UNIT_EN (1 << 7)
-#define HDMI_MODE_OUTPUT (1 << 0)
-#define HDMI_HBLANK_A 0x3100
-
-#define HDMI_AUDIO_CTRL 0x4000
-#define HDMI_ENABLE_AUDIO (1 << 0)
-
-#define PCH_HTOTAL_B 0x3100
-#define PCH_HBLANK_B 0x3104
-#define PCH_HSYNC_B 0x3108
-#define PCH_VTOTAL_B 0x310C
-#define PCH_VBLANK_B 0x3110
-#define PCH_VSYNC_B 0x3114
-#define PCH_PIPEBSRC 0x311C
-
-#define PCH_PIPEB_DSL 0x3800
-#define PCH_PIPEB_SLC 0x3804
-#define PCH_PIPEBCONF 0x3808
-#define PCH_PIPEBSTAT 0x3824
-
-#define CDVO_DFT 0x5000
-#define CDVO_SLEWRATE 0x5004
-#define CDVO_STRENGTH 0x5008
-#define CDVO_RCOMP 0x500C
-
-#define DPLL_CTRL 0x6000
-#define DPLL_PDIV_SHIFT 16
-#define DPLL_PDIV_MASK (0xf << 16)
-#define DPLL_PWRDN (1 << 4)
-#define DPLL_RESET (1 << 3)
-#define DPLL_FASTEN (1 << 2)
-#define DPLL_ENSTAT (1 << 1)
-#define DPLL_DITHEN (1 << 0)
-
-#define DPLL_DIV_CTRL 0x6004
-#define DPLL_CLKF_MASK 0xffffffc0
-#define DPLL_CLKR_MASK (0x3f)
-
-#define DPLL_CLK_ENABLE 0x6008
-#define DPLL_EN_DISP (1 << 31)
-#define DPLL_SEL_HDMI (1 << 8)
-#define DPLL_EN_HDMI (1 << 1)
-#define DPLL_EN_VGA (1 << 0)
-
-#define DPLL_ADJUST 0x600C
-#define DPLL_STATUS 0x6010
-#define DPLL_UPDATE 0x6014
-#define DPLL_DFT 0x6020
-
-struct intel_range {
- int min, max;
-};
-
-struct oaktrail_hdmi_limit {
- struct intel_range vco, np, nr, nf;
-};
-
-struct oaktrail_hdmi_clock {
- int np;
- int nr;
- int nf;
- int dot;
-};
-
-#define VCO_MIN 320000
-#define VCO_MAX 1650000
-#define NP_MIN 1
-#define NP_MAX 15
-#define NR_MIN 1
-#define NR_MAX 64
-#define NF_MIN 2
-#define NF_MAX 4095
-
-static const struct oaktrail_hdmi_limit oaktrail_hdmi_limit = {
- .vco = { .min = VCO_MIN, .max = VCO_MAX },
- .np = { .min = NP_MIN, .max = NP_MAX },
- .nr = { .min = NR_MIN, .max = NR_MAX },
- .nf = { .min = NF_MIN, .max = NF_MAX },
-};
-
-static void oaktrail_hdmi_audio_enable(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
-
- HDMI_WRITE(HDMI_HCR, 0x67);
- HDMI_READ(HDMI_HCR);
-
- HDMI_WRITE(0x51a8, 0x10);
- HDMI_READ(0x51a8);
-
- HDMI_WRITE(HDMI_AUDIO_CTRL, 0x1);
- HDMI_READ(HDMI_AUDIO_CTRL);
-}
-
-static void oaktrail_hdmi_audio_disable(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
-
- HDMI_WRITE(0x51a8, 0x0);
- HDMI_READ(0x51a8);
-
- HDMI_WRITE(HDMI_AUDIO_CTRL, 0x0);
- HDMI_READ(HDMI_AUDIO_CTRL);
-
- HDMI_WRITE(HDMI_HCR, 0x47);
- HDMI_READ(HDMI_HCR);
-}
-
-static unsigned int htotal_calculate(struct drm_display_mode *mode)
-{
- u32 new_crtc_htotal;
-
- /*
- * 1024 x 768 new_crtc_htotal = 0x1024;
- * 1280 x 1024 new_crtc_htotal = 0x0c34;
- */
- new_crtc_htotal = (mode->crtc_htotal - 1) * 200 * 1000 / mode->clock;
-
- DRM_DEBUG_KMS("new crtc htotal 0x%4x\n", new_crtc_htotal);
- return (mode->crtc_hdisplay - 1) | (new_crtc_htotal << 16);
-}
-
-static void oaktrail_hdmi_find_dpll(struct drm_crtc *crtc, int target,
- int refclk, struct oaktrail_hdmi_clock *best_clock)
-{
- int np_min, np_max, nr_min, nr_max;
- int np, nr, nf;
-
- np_min = DIV_ROUND_UP(oaktrail_hdmi_limit.vco.min, target * 10);
- np_max = oaktrail_hdmi_limit.vco.max / (target * 10);
- if (np_min < oaktrail_hdmi_limit.np.min)
- np_min = oaktrail_hdmi_limit.np.min;
- if (np_max > oaktrail_hdmi_limit.np.max)
- np_max = oaktrail_hdmi_limit.np.max;
-
- nr_min = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_max));
- nr_max = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_min));
- if (nr_min < oaktrail_hdmi_limit.nr.min)
- nr_min = oaktrail_hdmi_limit.nr.min;
- if (nr_max > oaktrail_hdmi_limit.nr.max)
- nr_max = oaktrail_hdmi_limit.nr.max;
-
- np = DIV_ROUND_UP((refclk * 1000), (target * 10 * nr_max));
- nr = DIV_ROUND_UP((refclk * 1000), (target * 10 * np));
- nf = DIV_ROUND_CLOSEST((target * 10 * np * nr), refclk);
- DRM_DEBUG_KMS("np, nr, nf %d %d %d\n", np, nr, nf);
-
- /*
- * 1024 x 768 np = 1; nr = 0x26; nf = 0x0fd8000;
- * 1280 x 1024 np = 1; nr = 0x17; nf = 0x1034000;
- */
- best_clock->np = np;
- best_clock->nr = nr - 1;
- best_clock->nf = (nf << 14);
-}
-
-static void scu_busy_loop(void __iomem *scu_base)
-{
- u32 status = 0;
- u32 loop_count = 0;
-
- status = readl(scu_base + 0x04);
- while (status & 1) {
- udelay(1); /* scu processing time is in few u secods */
- status = readl(scu_base + 0x04);
- loop_count++;
- /* break if scu doesn't reset busy bit after huge retry */
- if (loop_count > 1000) {
- DRM_DEBUG_KMS("SCU IPC timed out");
- return;
- }
- }
-}
-
-/*
- * You don't want to know, you really really don't want to know....
- *
- * This is magic. However it's safe magic because of the way the platform
- * works and it is necessary magic.
- */
-static void oaktrail_hdmi_reset(struct drm_device *dev)
-{
- void __iomem *base;
- unsigned long scu_ipc_mmio = 0xff11c000UL;
- int scu_len = 1024;
-
- base = ioremap((resource_size_t)scu_ipc_mmio, scu_len);
- if (base == NULL) {
- DRM_ERROR("failed to map scu mmio\n");
- return;
- }
-
- /* scu ipc: assert hdmi controller reset */
- writel(0xff11d118, base + 0x0c);
- writel(0x7fffffdf, base + 0x80);
- writel(0x42005, base + 0x0);
- scu_busy_loop(base);
-
- /* scu ipc: de-assert hdmi controller reset */
- writel(0xff11d118, base + 0x0c);
- writel(0x7fffffff, base + 0x80);
- writel(0x42005, base + 0x0);
- scu_busy_loop(base);
-
- iounmap(base);
-}
-
-int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode,
- int x, int y,
- struct drm_framebuffer *old_fb)
-{
- struct drm_device *dev = crtc->dev;
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
- int pipe = 1;
- int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
- int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
- int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
- int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
- int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
- int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
- int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
- int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
- int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
- int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
- int refclk;
- struct oaktrail_hdmi_clock clock;
- u32 dspcntr, pipeconf, dpll, temp;
- int dspcntr_reg = DSPBCNTR;
-
- if (!gma_power_begin(dev, true))
- return 0;
-
- /* Disable the VGA plane that we never use */
- REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
-
- /* Disable dpll if necessary */
- dpll = REG_READ(DPLL_CTRL);
- if ((dpll & DPLL_PWRDN) == 0) {
- REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET));
- REG_WRITE(DPLL_DIV_CTRL, 0x00000000);
- REG_WRITE(DPLL_STATUS, 0x1);
- }
- udelay(150);
-
- /* Reset controller */
- oaktrail_hdmi_reset(dev);
-
- /* program and enable dpll */
- refclk = 25000;
- oaktrail_hdmi_find_dpll(crtc, adjusted_mode->clock, refclk, &clock);
-
- /* Set the DPLL */
- dpll = REG_READ(DPLL_CTRL);
- dpll &= ~DPLL_PDIV_MASK;
- dpll &= ~(DPLL_PWRDN | DPLL_RESET);
- REG_WRITE(DPLL_CTRL, 0x00000008);
- REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr));
- REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1));
- REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN));
- REG_WRITE(DPLL_UPDATE, 0x80000000);
- REG_WRITE(DPLL_CLK_ENABLE, 0x80050102);
- udelay(150);
-
- /* configure HDMI */
- HDMI_WRITE(0x1004, 0x1fd);
- HDMI_WRITE(0x2000, 0x1);
- HDMI_WRITE(0x2008, 0x0);
- HDMI_WRITE(0x3130, 0x8);
- HDMI_WRITE(0x101c, 0x1800810);
-
- temp = htotal_calculate(adjusted_mode);
- REG_WRITE(htot_reg, temp);
- REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
- REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
- REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16));
- REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16));
- REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
- REG_WRITE(pipesrc_reg, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
-
- REG_WRITE(PCH_HTOTAL_B, (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
- REG_WRITE(PCH_HBLANK_B, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
- REG_WRITE(PCH_HSYNC_B, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
- REG_WRITE(PCH_VTOTAL_B, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16));
- REG_WRITE(PCH_VBLANK_B, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16));
- REG_WRITE(PCH_VSYNC_B, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
- REG_WRITE(PCH_PIPEBSRC, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
-
- temp = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
- HDMI_WRITE(HDMI_HBLANK_A, ((adjusted_mode->crtc_hdisplay - 1) << 16) | temp);
-
- REG_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
- REG_WRITE(dsppos_reg, 0);
-
- /* Flush the plane changes */
- {
- const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
- crtc_funcs->mode_set_base(crtc, x, y, old_fb);
- }
-
- /* Set up the display plane register */
- dspcntr = REG_READ(dspcntr_reg);
- dspcntr |= DISPPLANE_GAMMA_ENABLE;
- dspcntr |= DISPPLANE_SEL_PIPE_B;
- dspcntr |= DISPLAY_PLANE_ENABLE;
-
- /* setup pipeconf */
- pipeconf = REG_READ(pipeconf_reg);
- pipeconf |= PIPEACONF_ENABLE;
-
- REG_WRITE(pipeconf_reg, pipeconf);
- REG_READ(pipeconf_reg);
-
- REG_WRITE(PCH_PIPEBCONF, pipeconf);
- REG_READ(PCH_PIPEBCONF);
- gma_wait_for_vblank(dev);
-
- REG_WRITE(dspcntr_reg, dspcntr);
- gma_wait_for_vblank(dev);
-
- gma_power_end(dev);
-
- return 0;
-}
-
-void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode)
-{
- struct drm_device *dev = crtc->dev;
- u32 temp;
-
- DRM_DEBUG_KMS("%s %d\n", __func__, mode);
-
- switch (mode) {
- case DRM_MODE_DPMS_OFF:
- REG_WRITE(VGACNTRL, 0x80000000);
-
- /* Disable plane */
- temp = REG_READ(DSPBCNTR);
- if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
- REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE);
- REG_READ(DSPBCNTR);
- /* Flush the plane changes */
- REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));
- REG_READ(DSPBSURF);
- }
-
- /* Disable pipe B */
- temp = REG_READ(PIPEBCONF);
- if ((temp & PIPEACONF_ENABLE) != 0) {
- REG_WRITE(PIPEBCONF, temp & ~PIPEACONF_ENABLE);
- REG_READ(PIPEBCONF);
- }
-
- /* Disable LNW Pipes, etc */
- temp = REG_READ(PCH_PIPEBCONF);
- if ((temp & PIPEACONF_ENABLE) != 0) {
- REG_WRITE(PCH_PIPEBCONF, temp & ~PIPEACONF_ENABLE);
- REG_READ(PCH_PIPEBCONF);
- }
-
- /* wait for pipe off */
- udelay(150);
-
- /* Disable dpll */
- temp = REG_READ(DPLL_CTRL);
- if ((temp & DPLL_PWRDN) == 0) {
- REG_WRITE(DPLL_CTRL, temp | (DPLL_PWRDN | DPLL_RESET));
- REG_WRITE(DPLL_STATUS, 0x1);
- }
-
- /* wait for dpll off */
- udelay(150);
-
- break;
- case DRM_MODE_DPMS_ON:
- case DRM_MODE_DPMS_STANDBY:
- case DRM_MODE_DPMS_SUSPEND:
- /* Enable dpll */
- temp = REG_READ(DPLL_CTRL);
- if ((temp & DPLL_PWRDN) != 0) {
- REG_WRITE(DPLL_CTRL, temp & ~(DPLL_PWRDN | DPLL_RESET));
- temp = REG_READ(DPLL_CLK_ENABLE);
- REG_WRITE(DPLL_CLK_ENABLE, temp | DPLL_EN_DISP | DPLL_SEL_HDMI | DPLL_EN_HDMI);
- REG_READ(DPLL_CLK_ENABLE);
- }
- /* wait for dpll warm up */
- udelay(150);
-
- /* Enable pipe B */
- temp = REG_READ(PIPEBCONF);
- if ((temp & PIPEACONF_ENABLE) == 0) {
- REG_WRITE(PIPEBCONF, temp | PIPEACONF_ENABLE);
- REG_READ(PIPEBCONF);
- }
-
- /* Enable LNW Pipe B */
- temp = REG_READ(PCH_PIPEBCONF);
- if ((temp & PIPEACONF_ENABLE) == 0) {
- REG_WRITE(PCH_PIPEBCONF, temp | PIPEACONF_ENABLE);
- REG_READ(PCH_PIPEBCONF);
- }
-
- gma_wait_for_vblank(dev);
-
- /* Enable plane */
- temp = REG_READ(DSPBCNTR);
- if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
- REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE);
- /* Flush the plane changes */
- REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));
- REG_READ(DSPBSURF);
- }
-
- gma_crtc_load_lut(crtc);
- }
-
- /* DSPARB */
- REG_WRITE(DSPARB, 0x00003fbf);
-
- /* FW1 */
- REG_WRITE(0x70034, 0x3f880a0a);
-
- /* FW2 */
- REG_WRITE(0x70038, 0x0b060808);
-
- /* FW4 */
- REG_WRITE(0x70050, 0x08030404);
-
- /* FW5 */
- REG_WRITE(0x70054, 0x04040404);
-
- /* LNC Chicken Bits - Squawk! */
- REG_WRITE(0x70400, 0x4000);
-
- return;
-}
-
-static void oaktrail_hdmi_dpms(struct drm_encoder *encoder, int mode)
-{
- static int dpms_mode = -1;
-
- struct drm_device *dev = encoder->dev;
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
- u32 temp;
-
- if (dpms_mode == mode)
- return;
-
- if (mode != DRM_MODE_DPMS_ON)
- temp = 0x0;
- else
- temp = 0x99;
-
- dpms_mode = mode;
- HDMI_WRITE(HDMI_VIDEO_REG, temp);
-}
-
-static enum drm_mode_status oaktrail_hdmi_mode_valid(struct drm_connector *connector,
- struct drm_display_mode *mode)
-{
- if (mode->clock > 165000)
- return MODE_CLOCK_HIGH;
- if (mode->clock < 20000)
- return MODE_CLOCK_LOW;
-
- if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
- return MODE_NO_DBLESCAN;
-
- return MODE_OK;
-}
-
-static enum drm_connector_status
-oaktrail_hdmi_detect(struct drm_connector *connector, bool force)
-{
- enum drm_connector_status status;
- struct drm_device *dev = connector->dev;
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
- u32 temp;
-
- temp = HDMI_READ(HDMI_HSR);
- DRM_DEBUG_KMS("HDMI_HSR %x\n", temp);
-
- if ((temp & HDMI_DETECT_HDP) != 0)
- status = connector_status_connected;
- else
- status = connector_status_disconnected;
-
- return status;
-}
-
-static const unsigned char raw_edid[] = {
- 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x10, 0xac, 0x2f, 0xa0,
- 0x53, 0x55, 0x33, 0x30, 0x16, 0x13, 0x01, 0x03, 0x0e, 0x3a, 0x24, 0x78,
- 0xea, 0xe9, 0xf5, 0xac, 0x51, 0x30, 0xb4, 0x25, 0x11, 0x50, 0x54, 0xa5,
- 0x4b, 0x00, 0x81, 0x80, 0xa9, 0x40, 0x71, 0x4f, 0xb3, 0x00, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
- 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x46, 0x6c, 0x21, 0x00, 0x00, 0x1a,
- 0x00, 0x00, 0x00, 0xff, 0x00, 0x47, 0x4e, 0x37, 0x32, 0x31, 0x39, 0x35,
- 0x52, 0x30, 0x33, 0x55, 0x53, 0x0a, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x44,
- 0x45, 0x4c, 0x4c, 0x20, 0x32, 0x37, 0x30, 0x39, 0x57, 0x0a, 0x20, 0x20,
- 0x00, 0x00, 0x00, 0xfd, 0x00, 0x38, 0x4c, 0x1e, 0x53, 0x11, 0x00, 0x0a,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x8d
-};
-
-static int oaktrail_hdmi_get_modes(struct drm_connector *connector)
-{
- struct i2c_adapter *i2c_adap;
- struct edid *edid;
- int ret = 0;
-
- /*
- * FIXME: We need to figure this lot out. In theory we can
- * read the EDID somehow but I've yet to find working reference
- * code.
- */
- i2c_adap = i2c_get_adapter(3);
- if (i2c_adap == NULL) {
- DRM_ERROR("No ddc adapter available!\n");
- edid = (struct edid *)raw_edid;
- } else {
- edid = (struct edid *)raw_edid;
- /* FIXME ? edid = drm_get_edid(connector, i2c_adap); */
- }
-
- if (edid) {
- drm_connector_update_edid_property(connector, edid);
- ret = drm_add_edid_modes(connector, edid);
- }
- return ret;
-}
-
-static void oaktrail_hdmi_mode_set(struct drm_encoder *encoder,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- struct drm_device *dev = encoder->dev;
-
- oaktrail_hdmi_audio_enable(dev);
- return;
-}
-
-static void oaktrail_hdmi_destroy(struct drm_connector *connector)
-{
- return;
-}
-
-static const struct drm_encoder_helper_funcs oaktrail_hdmi_helper_funcs = {
- .dpms = oaktrail_hdmi_dpms,
- .prepare = gma_encoder_prepare,
- .mode_set = oaktrail_hdmi_mode_set,
- .commit = gma_encoder_commit,
-};
-
-static const struct drm_connector_helper_funcs
- oaktrail_hdmi_connector_helper_funcs = {
- .get_modes = oaktrail_hdmi_get_modes,
- .mode_valid = oaktrail_hdmi_mode_valid,
- .best_encoder = gma_best_encoder,
-};
-
-static const struct drm_connector_funcs oaktrail_hdmi_connector_funcs = {
- .dpms = drm_helper_connector_dpms,
- .detect = oaktrail_hdmi_detect,
- .fill_modes = drm_helper_probe_single_connector_modes,
- .destroy = oaktrail_hdmi_destroy,
-};
-
-void oaktrail_hdmi_init(struct drm_device *dev,
- struct psb_intel_mode_device *mode_dev)
-{
- struct gma_encoder *gma_encoder;
- struct gma_connector *gma_connector;
- struct drm_connector *connector;
- struct drm_encoder *encoder;
-
- gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
- if (!gma_encoder)
- return;
-
- gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
- if (!gma_connector)
- goto failed_connector;
-
- connector = &gma_connector->base;
- encoder = &gma_encoder->base;
- drm_connector_init(dev, connector,
- &oaktrail_hdmi_connector_funcs,
- DRM_MODE_CONNECTOR_DVID);
-
- drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_TMDS);
-
- gma_connector_attach_encoder(gma_connector, gma_encoder);
-
- gma_encoder->type = INTEL_OUTPUT_HDMI;
- drm_encoder_helper_add(encoder, &oaktrail_hdmi_helper_funcs);
- drm_connector_helper_add(connector, &oaktrail_hdmi_connector_helper_funcs);
-
- connector->display_info.subpixel_order = SubPixelHorizontalRGB;
- connector->interlace_allowed = false;
- connector->doublescan_allowed = false;
- drm_connector_register(connector);
- dev_info(dev->dev, "HDMI initialised.\n");
-
- return;
-
-failed_connector:
- kfree(gma_encoder);
-}
-
-void oaktrail_hdmi_setup(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct pci_dev *pdev;
- struct oaktrail_hdmi_dev *hdmi_dev;
- int ret;
-
- pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x080d, NULL);
- if (!pdev)
- return;
-
- hdmi_dev = kzalloc(sizeof(struct oaktrail_hdmi_dev), GFP_KERNEL);
- if (!hdmi_dev) {
- dev_err(dev->dev, "failed to allocate memory\n");
- goto out;
- }
-
-
- ret = pci_enable_device(pdev);
- if (ret) {
- dev_err(dev->dev, "failed to enable hdmi controller\n");
- goto free;
- }
-
- hdmi_dev->mmio = pci_resource_start(pdev, 0);
- hdmi_dev->mmio_len = pci_resource_len(pdev, 0);
- hdmi_dev->regs = ioremap(hdmi_dev->mmio, hdmi_dev->mmio_len);
- if (!hdmi_dev->regs) {
- dev_err(dev->dev, "failed to map hdmi mmio\n");
- goto free;
- }
-
- hdmi_dev->dev = pdev;
- pci_set_drvdata(pdev, hdmi_dev);
-
- /* Initialize i2c controller */
- ret = oaktrail_hdmi_i2c_init(hdmi_dev->dev);
- if (ret)
- dev_err(dev->dev, "HDMI I2C initialization failed\n");
-
- dev_priv->hdmi_priv = hdmi_dev;
- oaktrail_hdmi_audio_disable(dev);
-
- dev_info(dev->dev, "HDMI hardware present.\n");
-
- return;
-
-free:
- kfree(hdmi_dev);
-out:
- return;
-}
-
-void oaktrail_hdmi_teardown(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
- struct pci_dev *pdev;
-
- if (hdmi_dev) {
- pdev = hdmi_dev->dev;
- pci_set_drvdata(pdev, NULL);
- oaktrail_hdmi_i2c_exit(pdev);
- iounmap(hdmi_dev->regs);
- kfree(hdmi_dev);
- pci_dev_put(pdev);
- }
-}
-
-/* save HDMI register state */
-void oaktrail_hdmi_save(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
- struct psb_state *regs = &dev_priv->regs.psb;
- struct psb_pipe *pipeb = &dev_priv->regs.pipe[1];
- int i;
-
- /* dpll */
- hdmi_dev->saveDPLL_CTRL = PSB_RVDC32(DPLL_CTRL);
- hdmi_dev->saveDPLL_DIV_CTRL = PSB_RVDC32(DPLL_DIV_CTRL);
- hdmi_dev->saveDPLL_ADJUST = PSB_RVDC32(DPLL_ADJUST);
- hdmi_dev->saveDPLL_UPDATE = PSB_RVDC32(DPLL_UPDATE);
- hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE);
-
- /* pipe B */
- pipeb->conf = PSB_RVDC32(PIPEBCONF);
- pipeb->src = PSB_RVDC32(PIPEBSRC);
- pipeb->htotal = PSB_RVDC32(HTOTAL_B);
- pipeb->hblank = PSB_RVDC32(HBLANK_B);
- pipeb->hsync = PSB_RVDC32(HSYNC_B);
- pipeb->vtotal = PSB_RVDC32(VTOTAL_B);
- pipeb->vblank = PSB_RVDC32(VBLANK_B);
- pipeb->vsync = PSB_RVDC32(VSYNC_B);
-
- hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF);
- hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC);
- hdmi_dev->savePCH_HTOTAL_B = PSB_RVDC32(PCH_HTOTAL_B);
- hdmi_dev->savePCH_HBLANK_B = PSB_RVDC32(PCH_HBLANK_B);
- hdmi_dev->savePCH_HSYNC_B = PSB_RVDC32(PCH_HSYNC_B);
- hdmi_dev->savePCH_VTOTAL_B = PSB_RVDC32(PCH_VTOTAL_B);
- hdmi_dev->savePCH_VBLANK_B = PSB_RVDC32(PCH_VBLANK_B);
- hdmi_dev->savePCH_VSYNC_B = PSB_RVDC32(PCH_VSYNC_B);
-
- /* plane */
- pipeb->cntr = PSB_RVDC32(DSPBCNTR);
- pipeb->stride = PSB_RVDC32(DSPBSTRIDE);
- pipeb->addr = PSB_RVDC32(DSPBBASE);
- pipeb->surf = PSB_RVDC32(DSPBSURF);
- pipeb->linoff = PSB_RVDC32(DSPBLINOFF);
- pipeb->tileoff = PSB_RVDC32(DSPBTILEOFF);
-
- /* cursor B */
- regs->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR);
- regs->saveDSPBCURSOR_BASE = PSB_RVDC32(CURBBASE);
- regs->saveDSPBCURSOR_POS = PSB_RVDC32(CURBPOS);
-
- /* save palette */
- for (i = 0; i < 256; i++)
- pipeb->palette[i] = PSB_RVDC32(PALETTE_B + (i << 2));
-}
-
-/* restore HDMI register state */
-void oaktrail_hdmi_restore(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
- struct psb_state *regs = &dev_priv->regs.psb;
- struct psb_pipe *pipeb = &dev_priv->regs.pipe[1];
- int i;
-
- /* dpll */
- PSB_WVDC32(hdmi_dev->saveDPLL_CTRL, DPLL_CTRL);
- PSB_WVDC32(hdmi_dev->saveDPLL_DIV_CTRL, DPLL_DIV_CTRL);
- PSB_WVDC32(hdmi_dev->saveDPLL_ADJUST, DPLL_ADJUST);
- PSB_WVDC32(hdmi_dev->saveDPLL_UPDATE, DPLL_UPDATE);
- PSB_WVDC32(hdmi_dev->saveDPLL_CLK_ENABLE, DPLL_CLK_ENABLE);
- udelay(150);
-
- /* pipe */
- PSB_WVDC32(pipeb->src, PIPEBSRC);
- PSB_WVDC32(pipeb->htotal, HTOTAL_B);
- PSB_WVDC32(pipeb->hblank, HBLANK_B);
- PSB_WVDC32(pipeb->hsync, HSYNC_B);
- PSB_WVDC32(pipeb->vtotal, VTOTAL_B);
- PSB_WVDC32(pipeb->vblank, VBLANK_B);
- PSB_WVDC32(pipeb->vsync, VSYNC_B);
-
- PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC);
- PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B);
- PSB_WVDC32(hdmi_dev->savePCH_HBLANK_B, PCH_HBLANK_B);
- PSB_WVDC32(hdmi_dev->savePCH_HSYNC_B, PCH_HSYNC_B);
- PSB_WVDC32(hdmi_dev->savePCH_VTOTAL_B, PCH_VTOTAL_B);
- PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B);
- PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B);
-
- PSB_WVDC32(pipeb->conf, PIPEBCONF);
- PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF);
-
- /* plane */
- PSB_WVDC32(pipeb->linoff, DSPBLINOFF);
- PSB_WVDC32(pipeb->stride, DSPBSTRIDE);
- PSB_WVDC32(pipeb->tileoff, DSPBTILEOFF);
- PSB_WVDC32(pipeb->cntr, DSPBCNTR);
- PSB_WVDC32(pipeb->surf, DSPBSURF);
-
- /* cursor B */
- PSB_WVDC32(regs->saveDSPBCURSOR_CTRL, CURBCNTR);
- PSB_WVDC32(regs->saveDSPBCURSOR_POS, CURBPOS);
- PSB_WVDC32(regs->saveDSPBCURSOR_BASE, CURBBASE);
-
- /* restore palette */
- for (i = 0; i < 256; i++)
- PSB_WVDC32(pipeb->palette[i], PALETTE_B + (i << 2));
-}
diff --git a/drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c b/drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c
deleted file mode 100644
index fc9a34ed58bd..000000000000
--- a/drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c
+++ /dev/null
@@ -1,331 +0,0 @@
-/*
- * Copyright © 2010 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Li Peng <peng.li@xxxxxxxxx>
- */
-
-#include <linux/export.h>
-#include <linux/mutex.h>
-#include <linux/pci.h>
-#include <linux/i2c.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include "psb_drv.h"
-
-#define HDMI_READ(reg) readl(hdmi_dev->regs + (reg))
-#define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg))
-
-#define HDMI_HCR 0x1000
-#define HCR_DETECT_HDP (1 << 6)
-#define HCR_ENABLE_HDCP (1 << 5)
-#define HCR_ENABLE_AUDIO (1 << 2)
-#define HCR_ENABLE_PIXEL (1 << 1)
-#define HCR_ENABLE_TMDS (1 << 0)
-#define HDMI_HICR 0x1004
-#define HDMI_INTR_I2C_ERROR (1 << 4)
-#define HDMI_INTR_I2C_FULL (1 << 3)
-#define HDMI_INTR_I2C_DONE (1 << 2)
-#define HDMI_INTR_HPD (1 << 0)
-#define HDMI_HSR 0x1008
-#define HDMI_HISR 0x100C
-#define HDMI_HI2CRDB0 0x1200
-#define HDMI_HI2CHCR 0x1240
-#define HI2C_HDCP_WRITE (0 << 2)
-#define HI2C_HDCP_RI_READ (1 << 2)
-#define HI2C_HDCP_READ (2 << 2)
-#define HI2C_EDID_READ (3 << 2)
-#define HI2C_READ_CONTINUE (1 << 1)
-#define HI2C_ENABLE_TRANSACTION (1 << 0)
-
-#define HDMI_ICRH 0x1100
-#define HDMI_HI2CTDR0 0x1244
-#define HDMI_HI2CTDR1 0x1248
-
-#define I2C_STAT_INIT 0
-#define I2C_READ_DONE 1
-#define I2C_TRANSACTION_DONE 2
-
-struct hdmi_i2c_dev {
- struct i2c_adapter *adap;
- struct mutex i2c_lock;
- struct completion complete;
- int status;
- struct i2c_msg *msg;
- int buf_offset;
-};
-
-static void hdmi_i2c_irq_enable(struct oaktrail_hdmi_dev *hdmi_dev)
-{
- u32 temp;
-
- temp = HDMI_READ(HDMI_HICR);
- temp |= (HDMI_INTR_I2C_ERROR | HDMI_INTR_I2C_FULL | HDMI_INTR_I2C_DONE);
- HDMI_WRITE(HDMI_HICR, temp);
- HDMI_READ(HDMI_HICR);
-}
-
-static void hdmi_i2c_irq_disable(struct oaktrail_hdmi_dev *hdmi_dev)
-{
- HDMI_WRITE(HDMI_HICR, 0x0);
- HDMI_READ(HDMI_HICR);
-}
-
-static int xfer_read(struct i2c_adapter *adap, struct i2c_msg *pmsg)
-{
- struct oaktrail_hdmi_dev *hdmi_dev = i2c_get_adapdata(adap);
- struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
- u32 temp;
-
- i2c_dev->status = I2C_STAT_INIT;
- i2c_dev->msg = pmsg;
- i2c_dev->buf_offset = 0;
- reinit_completion(&i2c_dev->complete);
-
- /* Enable I2C transaction */
- temp = ((pmsg->len) << 20) | HI2C_EDID_READ | HI2C_ENABLE_TRANSACTION;
- HDMI_WRITE(HDMI_HI2CHCR, temp);
- HDMI_READ(HDMI_HI2CHCR);
-
- while (i2c_dev->status != I2C_TRANSACTION_DONE)
- wait_for_completion_interruptible_timeout(&i2c_dev->complete,
- 10 * HZ);
-
- return 0;
-}
-
-static int xfer_write(struct i2c_adapter *adap, struct i2c_msg *pmsg)
-{
- /*
- * XXX: i2c write seems isn't useful for EDID probe, don't do anything
- */
- return 0;
-}
-
-static int oaktrail_hdmi_i2c_access(struct i2c_adapter *adap,
- struct i2c_msg *pmsg,
- int num)
-{
- struct oaktrail_hdmi_dev *hdmi_dev = i2c_get_adapdata(adap);
- struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
- int i;
-
- mutex_lock(&i2c_dev->i2c_lock);
-
- /* Enable i2c unit */
- HDMI_WRITE(HDMI_ICRH, 0x00008760);
-
- /* Enable irq */
- hdmi_i2c_irq_enable(hdmi_dev);
- for (i = 0; i < num; i++) {
- if (pmsg->len && pmsg->buf) {
- if (pmsg->flags & I2C_M_RD)
- xfer_read(adap, pmsg);
- else
- xfer_write(adap, pmsg);
- }
- pmsg++; /* next message */
- }
-
- /* Disable irq */
- hdmi_i2c_irq_disable(hdmi_dev);
-
- mutex_unlock(&i2c_dev->i2c_lock);
-
- return i;
-}
-
-static u32 oaktrail_hdmi_i2c_func(struct i2c_adapter *adapter)
-{
- return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
-}
-
-static const struct i2c_algorithm oaktrail_hdmi_i2c_algorithm = {
- .master_xfer = oaktrail_hdmi_i2c_access,
- .functionality = oaktrail_hdmi_i2c_func,
-};
-
-static struct i2c_adapter oaktrail_hdmi_i2c_adapter = {
- .name = "oaktrail_hdmi_i2c",
- .nr = 3,
- .owner = THIS_MODULE,
- .class = I2C_CLASS_DDC,
- .algo = &oaktrail_hdmi_i2c_algorithm,
-};
-
-static void hdmi_i2c_read(struct oaktrail_hdmi_dev *hdmi_dev)
-{
- struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
- struct i2c_msg *msg = i2c_dev->msg;
- u8 *buf = msg->buf;
- u32 temp;
- int i, offset;
-
- offset = i2c_dev->buf_offset;
- for (i = 0; i < 0x10; i++) {
- temp = HDMI_READ(HDMI_HI2CRDB0 + (i * 4));
- memcpy(buf + (offset + i * 4), &temp, 4);
- }
- i2c_dev->buf_offset += (0x10 * 4);
-
- /* clearing read buffer full intr */
- temp = HDMI_READ(HDMI_HISR);
- HDMI_WRITE(HDMI_HISR, temp | HDMI_INTR_I2C_FULL);
- HDMI_READ(HDMI_HISR);
-
- /* continue read transaction */
- temp = HDMI_READ(HDMI_HI2CHCR);
- HDMI_WRITE(HDMI_HI2CHCR, temp | HI2C_READ_CONTINUE);
- HDMI_READ(HDMI_HI2CHCR);
-
- i2c_dev->status = I2C_READ_DONE;
- return;
-}
-
-static void hdmi_i2c_transaction_done(struct oaktrail_hdmi_dev *hdmi_dev)
-{
- struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
- u32 temp;
-
- /* clear transaction done intr */
- temp = HDMI_READ(HDMI_HISR);
- HDMI_WRITE(HDMI_HISR, temp | HDMI_INTR_I2C_DONE);
- HDMI_READ(HDMI_HISR);
-
-
- temp = HDMI_READ(HDMI_HI2CHCR);
- HDMI_WRITE(HDMI_HI2CHCR, temp & ~HI2C_ENABLE_TRANSACTION);
- HDMI_READ(HDMI_HI2CHCR);
-
- i2c_dev->status = I2C_TRANSACTION_DONE;
- return;
-}
-
-static irqreturn_t oaktrail_hdmi_i2c_handler(int this_irq, void *dev)
-{
- struct oaktrail_hdmi_dev *hdmi_dev = dev;
- struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
- u32 stat;
-
- stat = HDMI_READ(HDMI_HISR);
-
- if (stat & HDMI_INTR_HPD) {
- HDMI_WRITE(HDMI_HISR, stat | HDMI_INTR_HPD);
- HDMI_READ(HDMI_HISR);
- }
-
- if (stat & HDMI_INTR_I2C_FULL)
- hdmi_i2c_read(hdmi_dev);
-
- if (stat & HDMI_INTR_I2C_DONE)
- hdmi_i2c_transaction_done(hdmi_dev);
-
- complete(&i2c_dev->complete);
-
- return IRQ_HANDLED;
-}
-
-/*
- * choose alternate function 2 of GPIO pin 52, 53,
- * which is used by HDMI I2C logic
- */
-static void oaktrail_hdmi_i2c_gpio_fix(void)
-{
- void __iomem *base;
- unsigned int gpio_base = 0xff12c000;
- int gpio_len = 0x1000;
- u32 temp;
-
- base = ioremap((resource_size_t)gpio_base, gpio_len);
- if (base == NULL) {
- DRM_ERROR("gpio ioremap fail\n");
- return;
- }
-
- temp = readl(base + 0x44);
- DRM_DEBUG_DRIVER("old gpio val %x\n", temp);
- writel((temp | 0x00000a00), (base + 0x44));
- temp = readl(base + 0x44);
- DRM_DEBUG_DRIVER("new gpio val %x\n", temp);
-
- iounmap(base);
-}
-
-int oaktrail_hdmi_i2c_init(struct pci_dev *dev)
-{
- struct oaktrail_hdmi_dev *hdmi_dev;
- struct hdmi_i2c_dev *i2c_dev;
- int ret;
-
- hdmi_dev = pci_get_drvdata(dev);
-
- i2c_dev = kzalloc(sizeof(struct hdmi_i2c_dev), GFP_KERNEL);
- if (!i2c_dev)
- return -ENOMEM;
-
- i2c_dev->adap = &oaktrail_hdmi_i2c_adapter;
- i2c_dev->status = I2C_STAT_INIT;
- init_completion(&i2c_dev->complete);
- mutex_init(&i2c_dev->i2c_lock);
- i2c_set_adapdata(&oaktrail_hdmi_i2c_adapter, hdmi_dev);
- hdmi_dev->i2c_dev = i2c_dev;
-
- /* Enable HDMI I2C function on gpio */
- oaktrail_hdmi_i2c_gpio_fix();
-
- /* request irq */
- ret = request_irq(dev->irq, oaktrail_hdmi_i2c_handler, IRQF_SHARED,
- oaktrail_hdmi_i2c_adapter.name, hdmi_dev);
- if (ret) {
- DRM_ERROR("Failed to request IRQ for I2C controller\n");
- goto free_dev;
- }
-
- /* Adapter registration */
- ret = i2c_add_numbered_adapter(&oaktrail_hdmi_i2c_adapter);
- if (ret) {
- DRM_ERROR("Failed to add I2C adapter\n");
- goto free_irq;
- }
-
- return 0;
-
-free_irq:
- free_irq(dev->irq, hdmi_dev);
-free_dev:
- kfree(i2c_dev);
-
- return ret;
-}
-
-void oaktrail_hdmi_i2c_exit(struct pci_dev *dev)
-{
- struct oaktrail_hdmi_dev *hdmi_dev;
- struct hdmi_i2c_dev *i2c_dev;
-
- hdmi_dev = pci_get_drvdata(dev);
- i2c_del_adapter(&oaktrail_hdmi_i2c_adapter);
-
- i2c_dev = hdmi_dev->i2c_dev;
- kfree(i2c_dev);
- free_irq(dev->irq, hdmi_dev);
-}
diff --git a/drivers/gpu/drm/gma500/oaktrail_lvds.c b/drivers/gpu/drm/gma500/oaktrail_lvds.c
deleted file mode 100644
index 432bdcc57ac9..000000000000
--- a/drivers/gpu/drm/gma500/oaktrail_lvds.c
+++ /dev/null
@@ -1,423 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright © 2006-2009 Intel Corporation
- *
- * Authors:
- * Eric Anholt <eric@xxxxxxxxxx>
- * Dave Airlie <airlied@xxxxxxxx>
- * Jesse Barnes <jesse.barnes@xxxxxxxxx>
- */
-
-#include <linux/i2c.h>
-#include <linux/pm_runtime.h>
-
-#include <asm/intel-mid.h>
-
-#include <drm/drm_simple_kms_helper.h>
-
-#include "intel_bios.h"
-#include "power.h"
-#include "psb_drv.h"
-#include "psb_intel_drv.h"
-#include "psb_intel_reg.h"
-
-/* The max/min PWM frequency in BPCR[31:17] - */
-/* The smallest number is 1 (not 0) that can fit in the
- * 15-bit field of the and then*/
-/* shifts to the left by one bit to get the actual 16-bit
- * value that the 15-bits correspond to.*/
-#define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
-#define BRIGHTNESS_MAX_LEVEL 100
-
-/*
- * Sets the power state for the panel.
- */
-static void oaktrail_lvds_set_power(struct drm_device *dev,
- struct gma_encoder *gma_encoder,
- bool on)
-{
- u32 pp_status;
- struct drm_psb_private *dev_priv = dev->dev_private;
-
- if (!gma_power_begin(dev, true))
- return;
-
- if (on) {
- REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
- POWER_TARGET_ON);
- do {
- pp_status = REG_READ(PP_STATUS);
- } while ((pp_status & (PP_ON | PP_READY)) == PP_READY);
- dev_priv->is_lvds_on = true;
- if (dev_priv->ops->lvds_bl_power)
- dev_priv->ops->lvds_bl_power(dev, true);
- } else {
- if (dev_priv->ops->lvds_bl_power)
- dev_priv->ops->lvds_bl_power(dev, false);
- REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
- ~POWER_TARGET_ON);
- do {
- pp_status = REG_READ(PP_STATUS);
- } while (pp_status & PP_ON);
- dev_priv->is_lvds_on = false;
- pm_request_idle(dev->dev);
- }
- gma_power_end(dev);
-}
-
-static void oaktrail_lvds_dpms(struct drm_encoder *encoder, int mode)
-{
- struct drm_device *dev = encoder->dev;
- struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
-
- if (mode == DRM_MODE_DPMS_ON)
- oaktrail_lvds_set_power(dev, gma_encoder, true);
- else
- oaktrail_lvds_set_power(dev, gma_encoder, false);
-
- /* XXX: We never power down the LVDS pairs. */
-}
-
-static void oaktrail_lvds_mode_set(struct drm_encoder *encoder,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- struct drm_device *dev = encoder->dev;
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
- struct drm_mode_config *mode_config = &dev->mode_config;
- struct drm_connector *connector = NULL;
- struct drm_crtc *crtc = encoder->crtc;
- u32 lvds_port;
- uint64_t v = DRM_MODE_SCALE_FULLSCREEN;
-
- if (!gma_power_begin(dev, true))
- return;
-
- /*
- * The LVDS pin pair will already have been turned on in the
- * psb_intel_crtc_mode_set since it has a large impact on the DPLL
- * settings.
- */
- lvds_port = (REG_READ(LVDS) &
- (~LVDS_PIPEB_SELECT)) |
- LVDS_PORT_EN |
- LVDS_BORDER_EN;
-
- /* If the firmware says dither on Moorestown, or the BIOS does
- on Oaktrail then enable dithering */
- if (mode_dev->panel_wants_dither || dev_priv->lvds_dither)
- lvds_port |= MRST_PANEL_8TO6_DITHER_ENABLE;
-
- REG_WRITE(LVDS, lvds_port);
-
- /* Find the connector we're trying to set up */
- list_for_each_entry(connector, &mode_config->connector_list, head) {
- if (!connector->encoder || connector->encoder->crtc != crtc)
- continue;
- }
-
- if (!connector) {
- DRM_ERROR("Couldn't find connector when setting mode");
- gma_power_end(dev);
- return;
- }
-
- drm_object_property_get_value(
- &connector->base,
- dev->mode_config.scaling_mode_property,
- &v);
-
- if (v == DRM_MODE_SCALE_NO_SCALE)
- REG_WRITE(PFIT_CONTROL, 0);
- else if (v == DRM_MODE_SCALE_ASPECT) {
- if ((mode->vdisplay != adjusted_mode->crtc_vdisplay) ||
- (mode->hdisplay != adjusted_mode->crtc_hdisplay)) {
- if ((adjusted_mode->crtc_hdisplay * mode->vdisplay) ==
- (mode->hdisplay * adjusted_mode->crtc_vdisplay))
- REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
- else if ((adjusted_mode->crtc_hdisplay *
- mode->vdisplay) > (mode->hdisplay *
- adjusted_mode->crtc_vdisplay))
- REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
- PFIT_SCALING_MODE_PILLARBOX);
- else
- REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
- PFIT_SCALING_MODE_LETTERBOX);
- } else
- REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
- } else /*(v == DRM_MODE_SCALE_FULLSCREEN)*/
- REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
-
- gma_power_end(dev);
-}
-
-static void oaktrail_lvds_prepare(struct drm_encoder *encoder)
-{
- struct drm_device *dev = encoder->dev;
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
- struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
-
- if (!gma_power_begin(dev, true))
- return;
-
- mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
- mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL &
- BACKLIGHT_DUTY_CYCLE_MASK);
- oaktrail_lvds_set_power(dev, gma_encoder, false);
- gma_power_end(dev);
-}
-
-static u32 oaktrail_lvds_get_max_backlight(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- u32 ret;
-
- if (gma_power_begin(dev, false)) {
- ret = ((REG_READ(BLC_PWM_CTL) &
- BACKLIGHT_MODULATION_FREQ_MASK) >>
- BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
-
- gma_power_end(dev);
- } else
- ret = ((dev_priv->regs.saveBLC_PWM_CTL &
- BACKLIGHT_MODULATION_FREQ_MASK) >>
- BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
-
- return ret;
-}
-
-static void oaktrail_lvds_commit(struct drm_encoder *encoder)
-{
- struct drm_device *dev = encoder->dev;
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
- struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
-
- if (mode_dev->backlight_duty_cycle == 0)
- mode_dev->backlight_duty_cycle =
- oaktrail_lvds_get_max_backlight(dev);
- oaktrail_lvds_set_power(dev, gma_encoder, true);
-}
-
-static const struct drm_encoder_helper_funcs oaktrail_lvds_helper_funcs = {
- .dpms = oaktrail_lvds_dpms,
- .mode_fixup = psb_intel_lvds_mode_fixup,
- .prepare = oaktrail_lvds_prepare,
- .mode_set = oaktrail_lvds_mode_set,
- .commit = oaktrail_lvds_commit,
-};
-
-/* Returns the panel fixed mode from configuration. */
-
-static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev,
- struct psb_intel_mode_device *mode_dev)
-{
- struct drm_display_mode *mode = NULL;
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD;
-
- mode_dev->panel_fixed_mode = NULL;
-
- /* Use the firmware provided data on Moorestown */
- if (dev_priv->has_gct) {
- mode = kzalloc(sizeof(*mode), GFP_KERNEL);
- if (!mode)
- return;
-
- mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo;
- mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo;
- mode->hsync_start = mode->hdisplay + \
- ((ti->hsync_offset_hi << 8) | \
- ti->hsync_offset_lo);
- mode->hsync_end = mode->hsync_start + \
- ((ti->hsync_pulse_width_hi << 8) | \
- ti->hsync_pulse_width_lo);
- mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \
- ti->hblank_lo);
- mode->vsync_start = \
- mode->vdisplay + ((ti->vsync_offset_hi << 4) | \
- ti->vsync_offset_lo);
- mode->vsync_end = \
- mode->vsync_start + ((ti->vsync_pulse_width_hi << 4) | \
- ti->vsync_pulse_width_lo);
- mode->vtotal = mode->vdisplay + \
- ((ti->vblank_hi << 8) | ti->vblank_lo);
- mode->clock = ti->pixel_clock * 10;
-#if 0
- pr_info("hdisplay is %d\n", mode->hdisplay);
- pr_info("vdisplay is %d\n", mode->vdisplay);
- pr_info("HSS is %d\n", mode->hsync_start);
- pr_info("HSE is %d\n", mode->hsync_end);
- pr_info("htotal is %d\n", mode->htotal);
- pr_info("VSS is %d\n", mode->vsync_start);
- pr_info("VSE is %d\n", mode->vsync_end);
- pr_info("vtotal is %d\n", mode->vtotal);
- pr_info("clock is %d\n", mode->clock);
-#endif
- mode_dev->panel_fixed_mode = mode;
- }
-
- /* Use the BIOS VBT mode if available */
- if (mode_dev->panel_fixed_mode == NULL && mode_dev->vbt_mode)
- mode_dev->panel_fixed_mode = drm_mode_duplicate(dev,
- mode_dev->vbt_mode);
-
- /* Then try the LVDS VBT mode */
- if (mode_dev->panel_fixed_mode == NULL)
- if (dev_priv->lfp_lvds_vbt_mode)
- mode_dev->panel_fixed_mode =
- drm_mode_duplicate(dev,
- dev_priv->lfp_lvds_vbt_mode);
-
- /* If we still got no mode then bail */
- if (mode_dev->panel_fixed_mode == NULL)
- return;
-
- drm_mode_set_name(mode_dev->panel_fixed_mode);
- drm_mode_set_crtcinfo(mode_dev->panel_fixed_mode, 0);
-}
-
-/**
- * oaktrail_lvds_init - setup LVDS connectors on this device
- * @dev: drm device
- * @mode_dev: PSB mode device
- *
- * Create the connector, register the LVDS DDC bus, and try to figure out what
- * modes we can display on the LVDS panel (if present).
- */
-void oaktrail_lvds_init(struct drm_device *dev,
- struct psb_intel_mode_device *mode_dev)
-{
- struct gma_encoder *gma_encoder;
- struct gma_connector *gma_connector;
- struct drm_connector *connector;
- struct drm_encoder *encoder;
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct edid *edid;
- struct i2c_adapter *i2c_adap;
- struct drm_display_mode *scan; /* *modes, *bios_mode; */
-
- gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
- if (!gma_encoder)
- return;
-
- gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
- if (!gma_connector)
- goto failed_connector;
-
- connector = &gma_connector->base;
- encoder = &gma_encoder->base;
- dev_priv->is_lvds_on = true;
- drm_connector_init(dev, connector,
- &psb_intel_lvds_connector_funcs,
- DRM_MODE_CONNECTOR_LVDS);
-
- drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_LVDS);
-
- gma_connector_attach_encoder(gma_connector, gma_encoder);
- gma_encoder->type = INTEL_OUTPUT_LVDS;
-
- drm_encoder_helper_add(encoder, &oaktrail_lvds_helper_funcs);
- drm_connector_helper_add(connector,
- &psb_intel_lvds_connector_helper_funcs);
- connector->display_info.subpixel_order = SubPixelHorizontalRGB;
- connector->interlace_allowed = false;
- connector->doublescan_allowed = false;
-
- drm_object_attach_property(&connector->base,
- dev->mode_config.scaling_mode_property,
- DRM_MODE_SCALE_FULLSCREEN);
- drm_object_attach_property(&connector->base,
- dev_priv->backlight_property,
- BRIGHTNESS_MAX_LEVEL);
-
- mode_dev->panel_wants_dither = false;
- if (dev_priv->has_gct)
- mode_dev->panel_wants_dither = (dev_priv->gct_data.
- Panel_Port_Control & MRST_PANEL_8TO6_DITHER_ENABLE);
- if (dev_priv->lvds_dither)
- mode_dev->panel_wants_dither = 1;
-
- /*
- * LVDS discovery:
- * 1) check for EDID on DDC
- * 2) check for VBT data
- * 3) check to see if LVDS is already on
- * if none of the above, no panel
- * 4) make sure lid is open
- * if closed, act like it's not there for now
- */
-
- edid = NULL;
- mutex_lock(&dev->mode_config.mutex);
- i2c_adap = i2c_get_adapter(dev_priv->ops->i2c_bus);
- if (i2c_adap)
- edid = drm_get_edid(connector, i2c_adap);
- if (edid == NULL && dev_priv->lpc_gpio_base) {
- oaktrail_lvds_i2c_init(encoder);
- if (gma_encoder->ddc_bus != NULL) {
- i2c_adap = &gma_encoder->ddc_bus->adapter;
- edid = drm_get_edid(connector, i2c_adap);
- }
- }
- /*
- * Attempt to get the fixed panel mode from DDC. Assume that the
- * preferred mode is the right one.
- */
- if (edid) {
- drm_connector_update_edid_property(connector, edid);
- drm_add_edid_modes(connector, edid);
- kfree(edid);
-
- list_for_each_entry(scan, &connector->probed_modes, head) {
- if (scan->type & DRM_MODE_TYPE_PREFERRED) {
- mode_dev->panel_fixed_mode =
- drm_mode_duplicate(dev, scan);
- goto out; /* FIXME: check for quirks */
- }
- }
- } else
- dev_err(dev->dev, "No ddc adapter available!\n");
- /*
- * If we didn't get EDID, try geting panel timing
- * from configuration data
- */
- oaktrail_lvds_get_configuration_mode(dev, mode_dev);
-
- if (mode_dev->panel_fixed_mode) {
- mode_dev->panel_fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
- goto out; /* FIXME: check for quirks */
- }
-
- /* If we still don't have a mode after all that, give up. */
- if (!mode_dev->panel_fixed_mode) {
- dev_err(dev->dev, "Found no modes on the lvds, ignoring the LVDS\n");
- goto failed_find;
- }
-
-out:
- mutex_unlock(&dev->mode_config.mutex);
-
- drm_connector_register(connector);
- return;
-
-failed_find:
- mutex_unlock(&dev->mode_config.mutex);
-
- dev_dbg(dev->dev, "No LVDS modes found, disabling.\n");
- if (gma_encoder->ddc_bus) {
- psb_intel_i2c_destroy(gma_encoder->ddc_bus);
- gma_encoder->ddc_bus = NULL;
- }
-
-/* failed_ddc: */
-
- drm_encoder_cleanup(encoder);
- drm_connector_cleanup(connector);
- kfree(gma_connector);
-failed_connector:
- kfree(gma_encoder);
-}
-
diff --git a/drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c b/drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c
deleted file mode 100644
index 1d2dd6ea1c71..000000000000
--- a/drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Copyright (c) 2002-2010, Intel Corporation.
- * Copyright (c) 2014 ATRON electronic GmbH
- * Author: Jan Safrata <jan.nikitenko@xxxxxxxxx>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-#include <linux/delay.h>
-#include <linux/i2c-algo-bit.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/types.h>
-
-#include "psb_drv.h"
-#include "psb_intel_reg.h"
-
-
-/*
- * LPC GPIO based I2C bus for LVDS of Atom E6xx
- */
-
-/*-----------------------------------------------------------------------------
- * LPC Register Offsets. Used for LVDS GPIO Bit Bashing. Registers are part
- * Atom E6xx [D31:F0]
- ----------------------------------------------------------------------------*/
-#define RGEN 0x20
-#define RGIO 0x24
-#define RGLVL 0x28
-#define RGTPE 0x2C
-#define RGTNE 0x30
-#define RGGPE 0x34
-#define RGSMI 0x38
-#define RGTS 0x3C
-
-/* The LVDS GPIO clock lines are GPIOSUS[3]
- * The LVDS GPIO data lines are GPIOSUS[4]
- */
-#define GPIO_CLOCK 0x08
-#define GPIO_DATA 0x10
-
-#define LPC_READ_REG(chan, r) inl((chan)->reg + (r))
-#define LPC_WRITE_REG(chan, r, val) outl((val), (chan)->reg + (r))
-
-static int get_clock(void *data)
-{
- struct psb_intel_i2c_chan *chan = data;
- u32 val;
-
- val = LPC_READ_REG(chan, RGIO);
- val |= GPIO_CLOCK;
- LPC_WRITE_REG(chan, RGIO, val);
- LPC_READ_REG(chan, RGLVL);
- val = (LPC_READ_REG(chan, RGLVL) & GPIO_CLOCK) ? 1 : 0;
-
- return val;
-}
-
-static int get_data(void *data)
-{
- struct psb_intel_i2c_chan *chan = data;
- u32 val;
-
- val = LPC_READ_REG(chan, RGIO);
- val |= GPIO_DATA;
- LPC_WRITE_REG(chan, RGIO, val);
- LPC_READ_REG(chan, RGLVL);
- val = (LPC_READ_REG(chan, RGLVL) & GPIO_DATA) ? 1 : 0;
-
- return val;
-}
-
-static void set_clock(void *data, int state_high)
-{
- struct psb_intel_i2c_chan *chan = data;
- u32 val;
-
- if (state_high) {
- val = LPC_READ_REG(chan, RGIO);
- val |= GPIO_CLOCK;
- LPC_WRITE_REG(chan, RGIO, val);
- } else {
- val = LPC_READ_REG(chan, RGIO);
- val &= ~GPIO_CLOCK;
- LPC_WRITE_REG(chan, RGIO, val);
- val = LPC_READ_REG(chan, RGLVL);
- val &= ~GPIO_CLOCK;
- LPC_WRITE_REG(chan, RGLVL, val);
- }
-}
-
-static void set_data(void *data, int state_high)
-{
- struct psb_intel_i2c_chan *chan = data;
- u32 val;
-
- if (state_high) {
- val = LPC_READ_REG(chan, RGIO);
- val |= GPIO_DATA;
- LPC_WRITE_REG(chan, RGIO, val);
- } else {
- val = LPC_READ_REG(chan, RGIO);
- val &= ~GPIO_DATA;
- LPC_WRITE_REG(chan, RGIO, val);
- val = LPC_READ_REG(chan, RGLVL);
- val &= ~GPIO_DATA;
- LPC_WRITE_REG(chan, RGLVL, val);
- }
-}
-
-void oaktrail_lvds_i2c_init(struct drm_encoder *encoder)
-{
- struct drm_device *dev = encoder->dev;
- struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct psb_intel_i2c_chan *chan;
-
- chan = kzalloc(sizeof(struct psb_intel_i2c_chan), GFP_KERNEL);
- if (!chan)
- return;
-
- chan->drm_dev = dev;
- chan->reg = dev_priv->lpc_gpio_base;
- strncpy(chan->adapter.name, "gma500 LPC", I2C_NAME_SIZE - 1);
- chan->adapter.owner = THIS_MODULE;
- chan->adapter.algo_data = &chan->algo;
- chan->adapter.dev.parent = dev->dev;
- chan->algo.setsda = set_data;
- chan->algo.setscl = set_clock;
- chan->algo.getsda = get_data;
- chan->algo.getscl = get_clock;
- chan->algo.udelay = 100;
- chan->algo.timeout = usecs_to_jiffies(2200);
- chan->algo.data = chan;
-
- i2c_set_adapdata(&chan->adapter, chan);
-
- set_data(chan, 1);
- set_clock(chan, 1);
- udelay(50);
-
- if (i2c_bit_add_bus(&chan->adapter)) {
- kfree(chan);
- return;
- }
-
- gma_encoder->ddc_bus = chan;
-}
diff --git a/drivers/gpu/drm/gma500/psb_drv.c b/drivers/gpu/drm/gma500/psb_drv.c
index b083b3f815b9..c3653975a6c4 100644
--- a/drivers/gpu/drm/gma500/psb_drv.c
+++ b/drivers/gpu/drm/gma500/psb_drv.c
@@ -28,7 +28,6 @@
#include "framebuffer.h"
#include "intel_bios.h"
-#include "mid_bios.h"
#include "power.h"
#include "psb_drv.h"
#include "psb_intel_reg.h"
@@ -44,8 +43,6 @@ static int psb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
* 0x8086 = Intel Corporation
*
* PowerVR SGX535 - Poulsbo - Intel GMA 500, Intel Atom Z5xx
- * PowerVR SGX535 - Moorestown - Intel GMA 600
- * PowerVR SGX535 - Oaktrail - Intel GMA 600, Intel Atom Z6xx, E6xx
* PowerVR SGX545 - Cedartrail - Intel GMA 3600, Intel Atom D2500, N2600
* PowerVR SGX545 - Cedartrail - Intel GMA 3650, Intel Atom D2550, D2700,
* N2800
@@ -53,17 +50,6 @@ static int psb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
static const struct pci_device_id pciidlist[] = {
{ 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
{ 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
-#if defined(CONFIG_DRM_GMA600)
- { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
- { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
- { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
- { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
- { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
- { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
- { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
- { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
- { 0x8086, 0x4108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
-#endif
#if defined(CONFIG_DRM_GMA3600)
{ 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
{ 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
@@ -182,8 +168,6 @@ static void psb_driver_unload(struct drm_device *dev)
iounmap(dev_priv->aux_reg);
dev_priv->aux_reg = NULL;
}
- pci_dev_put(dev_priv->aux_pdev);
- pci_dev_put(dev_priv->lpc_pdev);
/* Destroy VBT data */
psb_intel_destroy_bios(dev);
@@ -198,7 +182,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags)
{
struct pci_dev *pdev = to_pci_dev(dev->dev);
struct drm_psb_private *dev_priv;
- unsigned long resource_start, resource_len;
+ unsigned long resource_start;
unsigned long irqflags;
int ret = -ENOMEM;
struct drm_connector *connector;
@@ -232,53 +216,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags)
if (!dev_priv->sgx_reg)
goto out_err;
- if (IS_MRST(dev)) {
- int domain = pci_domain_nr(pdev->bus);
-
- dev_priv->aux_pdev =
- pci_get_domain_bus_and_slot(domain, 0,
- PCI_DEVFN(3, 0));
-
- if (dev_priv->aux_pdev) {
- resource_start = pci_resource_start(dev_priv->aux_pdev,
- PSB_AUX_RESOURCE);
- resource_len = pci_resource_len(dev_priv->aux_pdev,
- PSB_AUX_RESOURCE);
- dev_priv->aux_reg = ioremap(resource_start,
- resource_len);
- if (!dev_priv->aux_reg)
- goto out_err;
-
- DRM_DEBUG_KMS("Found aux vdc");
- } else {
- /* Couldn't find the aux vdc so map to primary vdc */
- dev_priv->aux_reg = dev_priv->vdc_reg;
- DRM_DEBUG_KMS("Couldn't find aux pci device");
- }
- dev_priv->gmbus_reg = dev_priv->aux_reg;
-
- dev_priv->lpc_pdev =
- pci_get_domain_bus_and_slot(domain, 0,
- PCI_DEVFN(31, 0));
- if (dev_priv->lpc_pdev) {
- pci_read_config_word(dev_priv->lpc_pdev, PSB_LPC_GBA,
- &dev_priv->lpc_gpio_base);
- pci_write_config_dword(dev_priv->lpc_pdev, PSB_LPC_GBA,
- (u32)dev_priv->lpc_gpio_base | (1L<<31));
- pci_read_config_word(dev_priv->lpc_pdev, PSB_LPC_GBA,
- &dev_priv->lpc_gpio_base);
- dev_priv->lpc_gpio_base &= 0xffc0;
- if (dev_priv->lpc_gpio_base)
- DRM_DEBUG_KMS("Found LPC GPIO at 0x%04x\n",
- dev_priv->lpc_gpio_base);
- else {
- pci_dev_put(dev_priv->lpc_pdev);
- dev_priv->lpc_pdev = NULL;
- }
- }
- } else {
- dev_priv->gmbus_reg = dev_priv->vdc_reg;
- }
+ dev_priv->gmbus_reg = dev_priv->vdc_reg;
psb_intel_opregion_setup(dev);
diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
index 020a71b91577..0f82a2fc5ded 100644
--- a/drivers/gpu/drm/gma500/psb_drv.h
+++ b/drivers/gpu/drm/gma500/psb_drv.h
@@ -17,7 +17,6 @@
#include "gtt.h"
#include "intel_bios.h"
#include "mmu.h"
-#include "oaktrail.h"
#include "opregion.h"
#include "power.h"
#include "psb_intel_drv.h"
@@ -39,17 +38,14 @@
enum {
CHIP_PSB_8108 = 0, /* Poulsbo */
CHIP_PSB_8109 = 1, /* Poulsbo */
- CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
};
#define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108)
-#define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100)
#define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0)
/* Hardware offsets */
#define PSB_VDC_OFFSET 0x00000000
#define PSB_VDC_SIZE 0x000080000
-#define MRST_MMIO_SIZE 0x0000C0000
#define PSB_SGX_SIZE 0x8000
#define PSB_SGX_OFFSET 0x00040000
#define MRST_SGX_OFFSET 0x00080000
@@ -388,8 +384,6 @@ struct psb_ops;
struct drm_psb_private {
struct drm_device *dev;
- struct pci_dev *aux_pdev; /* Currently only used by mrst */
- struct pci_dev *lpc_pdev; /* Currently only used by mrst */
const struct psb_ops *ops;
const struct psb_offset *regmap;
@@ -494,13 +488,6 @@ struct drm_psb_private {
/* Runtime PM state */
int rpm_enabled;
- /* MID specific */
- bool has_gct;
- struct oaktrail_gct_data gct_data;
-
- /* Oaktrail HDMI state */
- struct oaktrail_hdmi_dev *hdmi_priv;
-
/* Register state */
struct psb_save_area regs;
@@ -667,13 +654,6 @@ void gma_backlight_disable(struct drm_device *dev);
void gma_backlight_enable(struct drm_device *dev);
void gma_backlight_set(struct drm_device *dev, int v);
-/* oaktrail_crtc.c */
-extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
-
-/* oaktrail_lvds.c */
-extern void oaktrail_lvds_init(struct drm_device *dev,
- struct psb_intel_mode_device *mode_dev);
-
/* psb_intel_display.c */
extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
@@ -690,9 +670,6 @@ extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
/* psb_device.c */
extern const struct psb_ops psb_chip_ops;
-/* oaktrail_device.c */
-extern const struct psb_ops oaktrail_chip_ops;
-
/* cdv_device.c */
extern const struct psb_ops cdv_chip_ops;
@@ -713,25 +690,6 @@ extern const struct psb_ops cdv_chip_ops;
extern int drm_idle_check_interval;
/* Utilities */
-static inline u32 MRST_MSG_READ32(int domain, uint port, uint offset)
-{
- int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
- uint32_t ret_val = 0;
- struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
- pci_write_config_dword(pci_root, 0xD0, mcr);
- pci_read_config_dword(pci_root, 0xD4, &ret_val);
- pci_dev_put(pci_root);
- return ret_val;
-}
-static inline void MRST_MSG_WRITE32(int domain, uint port, uint offset,
- u32 value)
-{
- int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
- struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
- pci_write_config_dword(pci_root, 0xD4, value);
- pci_write_config_dword(pci_root, 0xD0, mcr);
- pci_dev_put(pci_root);
-}
static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
{
diff --git a/drivers/gpu/drm/gma500/psb_intel_drv.h b/drivers/gpu/drm/gma500/psb_intel_drv.h
index 5340225d6997..1d62e541a9d7 100644
--- a/drivers/gpu/drm/gma500/psb_intel_drv.h
+++ b/drivers/gpu/drm/gma500/psb_intel_drv.h
@@ -192,12 +192,6 @@ extern void psb_intel_tv_init(struct drm_device *dev);
extern void psb_intel_lvds_init(struct drm_device *dev,
struct psb_intel_mode_device *mode_dev);
extern void psb_intel_lvds_set_brightness(struct drm_device *dev, int level);
-extern void oaktrail_lvds_init(struct drm_device *dev,
- struct psb_intel_mode_device *mode_dev);
-extern void oaktrail_wait_for_INTR_PKT_SENT(struct drm_device *dev);
-extern void oaktrail_dsi_init(struct drm_device *dev,
- struct psb_intel_mode_device *mode_dev);
-extern void oaktrail_lvds_i2c_init(struct drm_encoder *encoder);
extern void mid_dsi_init(struct drm_device *dev,
struct psb_intel_mode_device *mode_dev, int dsi_num);
diff --git a/drivers/gpu/drm/gma500/psb_intel_lvds.c b/drivers/gpu/drm/gma500/psb_intel_lvds.c
index ace95d4bdb6f..462ae5dc6a44 100644
--- a/drivers/gpu/drm/gma500/psb_intel_lvds.c
+++ b/drivers/gpu/drm/gma500/psb_intel_lvds.c
@@ -375,15 +375,11 @@ bool psb_intel_lvds_mode_fixup(struct drm_encoder *encoder,
if (gma_encoder->type == INTEL_OUTPUT_MIPI2)
panel_fixed_mode = mode_dev->panel_fixed_mode2;
- /* PSB requires the LVDS is on pipe B, MRST has only one pipe anyway */
- if (!IS_MRST(dev) && gma_crtc->pipe == 0) {
+ /* PSB requires the LVDS is on pipe B */
+ if (gma_crtc->pipe == 0) {
pr_err("Can't support LVDS on pipe A\n");
return false;
}
- if (IS_MRST(dev) && gma_crtc->pipe != 0) {
- pr_err("Must use PIPE A\n");
- return false;
- }
/* Should never happen!! */
list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list,
head) {
@@ -497,11 +493,9 @@ static int psb_intel_lvds_get_modes(struct drm_connector *connector)
struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
struct psb_intel_lvds_priv *lvds_priv = gma_encoder->dev_priv;
- int ret = 0;
-
- if (!IS_MRST(dev))
- ret = psb_intel_ddc_get_modes(connector, &lvds_priv->i2c_bus->adapter);
+ int ret;
+ ret = psb_intel_ddc_get_modes(connector, &lvds_priv->i2c_bus->adapter);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/gma500/psb_intel_reg.h b/drivers/gpu/drm/gma500/psb_intel_reg.h
index 364ea8f06f9c..74a5266275ef 100644
--- a/drivers/gpu/drm/gma500/psb_intel_reg.h
+++ b/drivers/gpu/drm/gma500/psb_intel_reg.h
@@ -785,15 +785,6 @@ struct dpst_guardband {
#define IMR 0x020a8
#define ISR 0x020ac
-/*
- * MOORESTOWN delta registers
- */
-#define MRST_DPLL_A 0x0f014
-#define DPLLA_MODE_LVDS (2 << 26) /* mrst */
-#define MRST_FPA0 0x0f040
-#define MRST_FPA1 0x0f044
-#define MRST_PERF_MODE 0x020f4
-
/*
* MEDFIELD HDMI registers
*/
@@ -806,8 +797,6 @@ struct dpst_guardband {
#define HDMIB_HDCP_PORT (1 << 5)
/* #define LVDS 0x61180 */
-#define MRST_PANEL_8TO6_DITHER_ENABLE (1 << 25)
-#define MRST_PANEL_24_DOT_1_FORMAT (1 << 24)
#define LVDS_A3_POWER_UP_0_OUTPUT (1 << 6)
#define MIPI 0x61190
@@ -831,16 +820,11 @@ struct dpst_guardband {
#define PFIT_PIPE_SELECT_SHIFT (29)
/* #define BLC_PWM_CTL 0x61254 */
-#define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT (16)
-#define MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16)
/* #define PIPEACONF 0x70008 */
#define PIPEACONF_PIPE_STATE (1 << 30)
/* #define DSPACNTR 0x70180 */
-#define MRST_DSPABASE 0x7019c
-#define MRST_DSPBBASE 0x7119c
-
/*
* Moorestown registers.
*/
diff --git a/drivers/gpu/drm/gma500/psb_intel_sdvo.c b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
index 355da2856389..7981d3a1545b 100644
--- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
+++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
@@ -231,9 +231,8 @@ static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u3
struct drm_device *dev = psb_intel_sdvo->base.base.dev;
u32 bval = val, cval = val;
int i, j;
- int need_aux = IS_MRST(dev) ? 1 : 0;
- for (j = 0; j <= need_aux; j++) {
+ for (j = 0; j < 1; j++) {
if (psb_intel_sdvo->sdvo_reg == SDVOB)
cval = REG_READ_WITH_AUX(SDVOC, j);
else
@@ -975,7 +974,6 @@ static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder,
struct psb_intel_sdvo_in_out_map in_out;
struct psb_intel_sdvo_dtd input_dtd;
int rate;
- int need_aux = IS_MRST(dev) ? 1 : 0;
if (!mode)
return;
@@ -1041,10 +1039,7 @@ static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder,
return;
/* Set the SDVO control regs. */
- if (need_aux)
- sdvox = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
- else
- sdvox = REG_READ(psb_intel_sdvo->sdvo_reg);
+ sdvox = REG_READ(psb_intel_sdvo->sdvo_reg);
switch (psb_intel_sdvo->sdvo_reg) {
case SDVOB:
@@ -1076,7 +1071,6 @@ static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
u32 temp;
int i;
- int need_aux = IS_MRST(dev) ? 1 : 0;
switch (mode) {
case DRM_MODE_DPMS_ON:
@@ -1095,10 +1089,7 @@ static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
if (mode == DRM_MODE_DPMS_OFF) {
- if (need_aux)
- temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
- else
- temp = REG_READ(psb_intel_sdvo->sdvo_reg);
+ temp = REG_READ(psb_intel_sdvo->sdvo_reg);
if ((temp & SDVO_ENABLE) != 0) {
psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & ~SDVO_ENABLE);
@@ -1108,10 +1099,7 @@ static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
bool input1, input2;
u8 status;
- if (need_aux)
- temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
- else
- temp = REG_READ(psb_intel_sdvo->sdvo_reg);
+ temp = REG_READ(psb_intel_sdvo->sdvo_reg);
if ((temp & SDVO_ENABLE) == 0)
psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE);
--
2.30.0
_______________________________________________
dri-devel mailing list
dri-devel@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/dri-devel
