On Fri, 2021-01-08 at 15:58 +0000, Steven Price wrote: > On 05/01/2021 05:36, Nick Fan wrote: > > Add a basic GPU node for mt8192. > > > > Signed-off-by: Nick Fan <Nick.Fan@xxxxxxxxxxxx> > > --- > > This patch depends on Mediatek power and regulator support. > > > > Listed as following. > > > > [1]https://lore.kernel.org/patchwork/patch/1336293/ > > [2]https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013 > > [3]https://lore.kernel.org/patchwork/patch/1356037/ > > [4]https://patchwork.kernel.org/project/linux-mediatek/list/?series=405777 > > [5]https://lore.kernel.org/patchwork/patch/1356175/ > > [6]https://patchwork.kernel.org/project/linux-mediatek/patch/1605700894-32699-6-git-send-email-hsin-hsiung.wang@xxxxxxxxxxxx/ > > [7]https://patchwork.kernel.org/project/linux-mediatek/patch/1608104827-7937-10-git-send-email-hsin-hsiung.wang@xxxxxxxxxxxx/ > > --- > > --- > > arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 + > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 176 ++++++++++++++++++++ > > 2 files changed, 183 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts > > index 6c1e2b3e8a60..48c0e240dd92 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts > > +++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts > > @@ -5,6 +5,7 @@ > > */ > > /dts-v1/; > > #include "mt8192.dtsi" > > +#include "mt6359.dtsi" > > > > / { > > model = "MediaTek MT8192 evaluation board"; > > @@ -70,6 +71,12 @@ > > }; > > }; > > > > +&gpu { > > + supply-names = "mali","sram"; > > + mali-supply = <&mt6315_7_vbuck1>; > > + sram-supply = <&mt6359_vsram_others_ldo_reg>; > > +}; > > + > > &uart0 { > > status = "okay"; > > }; > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > index d6a4ad242a33..de166ea750af 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > @@ -822,6 +822,182 @@ > > #clock-cells = <1>; > > }; > > > > + gpu: mali@13000000 { > > + compatible = "mediatek,mt8192-mali", "arm,mali-valhall"; > > + reg = <0 0x13000000 0 0x4000>; > > + interrupts = > > + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>, > > + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>, > > + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>, > > + <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 0>, > > + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>; > > + interrupt-names = > > + "GPU", > > + "MMU", > > + "JOB", > > + "EVENT", > > + "PWR"; > > These interrupt names don't match the binding you've posted (GPU, MMU, > JOB are upper case here, lower case in the binding). Also EVENT and PWR > are not mentioned in the binding - should they be? > > I know there are differences here between kbase's requirements and the > existing upstream bindings (case specifically), but I haven't seen a > binding containing EVENT and PWR before. > > Steve > Thanks for your comment. Yes, the EVENT and PWR should be removed. And the rest of interrupt names are corrected to lower case. Please check my updated version 4 for this. https://lore.kernel.org/patchwork/patch/1363862/ Nick Fan > > + > > + clocks = > > + <&apmixedsys CLK_APMIXED_MFGPLL>, > > + <&topckgen CLK_TOP_MFG_PLL_SEL>, > > + <&topckgen CLK_TOP_MFG_REF_SEL>, > > + <&mfgcfg CLK_MFG_BG3D>; > > + clock-names = > > + "clk_main_parent", > > + "clk_mux", > > + "clk_sub_parent", > > + "subsys_mfg_cg"; > > + > > + power-domains = > > + <&scpsys MT8192_POWER_DOMAIN_MFG2>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG3>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG4>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG5>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG6>; > > + power-domain-names = "core0", > > + "core1", > > + "core2", > > + "core3", > > + "core4"; > > + > > + operating-points-v2 = <&gpu_opp_table>; > > + #cooling-cells = <2>; > > + }; > > + > > + gpu_opp_table: opp_table0 { > > + compatible = "operating-points-v2"; > > + opp-shared; > > + > > + opp-358000000 { > > + opp-hz = /bits/ 64 <358000000>; > > + opp-hz-real = /bits/ 64 <358000000>, > > + /bits/ 64 <358000000>; > > + opp-microvolt = <606250>, > > + <750000>; > > + }; > > + > > + opp-399000000 { > > + opp-hz = /bits/ 64 <399000000>; > > + opp-hz-real = /bits/ 64 <399000000>, > > + /bits/ 64 <399000000>; > > + opp-microvolt = <618750>, > > + <750000>; > > + }; > > + > > + opp-440000000 { > > + opp-hz = /bits/ 64 <440000000>; > > + opp-hz-real = /bits/ 64 <440000000>, > > + /bits/ 64 <440000000>; > > + opp-microvolt = <631250>, > > + <750000>; > > + }; > > + > > + opp-482000000 { > > + opp-hz = /bits/ 64 <482000000>; > > + opp-hz-real = /bits/ 64 <482000000>, > > + /bits/ 64 <482000000>; > > + opp-microvolt = <643750>, > > + <750000>; > > + }; > > + > > + opp-523000000 { > > + opp-hz = /bits/ 64 <523000000>; > > + opp-hz-real = /bits/ 64 <523000000>, > > + /bits/ 64 <523000000>; > > + opp-microvolt = <656250>, > > + <750000>; > > + }; > > + > > + opp-564000000 { > > + opp-hz = /bits/ 64 <564000000>; > > + opp-hz-real = /bits/ 64 <564000000>, > > + /bits/ 64 <564000000>; > > + opp-microvolt = <668750>, > > + <750000>; > > + }; > > + > > + opp-605000000 { > > + opp-hz = /bits/ 64 <605000000>; > > + opp-hz-real = /bits/ 64 <605000000>, > > + /bits/ 64 <605000000>; > > + opp-microvolt = <681250>, > > + <750000>; > > + }; > > + > > + opp-647000000 { > > + opp-hz = /bits/ 64 <647000000>; > > + opp-hz-real = /bits/ 64 <647000000>, > > + /bits/ 64 <647000000>; > > + opp-microvolt = <693750>, > > + <750000>; > > + }; > > + > > + opp-688000000 { > > + opp-hz = /bits/ 64 <688000000>; > > + opp-hz-real = /bits/ 64 <688000000>, > > + /bits/ 64 <688000000>; > > + opp-microvolt = <706250>, > > + <750000>; > > + }; > > + > > + opp-724000000 { > > + opp-hz = /bits/ 64 <724000000>; > > + opp-hz-real = /bits/ 64 <724000000>, > > + /bits/ 64 <724000000>; > > + opp-microvolt = <725000>, > > + <750000>; > > + }; > > + > > + opp-760000000 { > > + opp-hz = /bits/ 64 <760000000>; > > + opp-hz-real = /bits/ 64 <760000000>, > > + /bits/ 64 <760000000>; > > + opp-microvolt = <743750>, > > + <750000>; > > + }; > > + > > + opp-795000000 { > > + opp-hz = /bits/ 64 <795000000>; > > + opp-hz-real = /bits/ 64 <795000000>, > > + /bits/ 64 <795000000>; > > + opp-microvolt = <762500>, > > + <762500>; > > + }; > > + > > + opp-831000000 { > > + opp-hz = /bits/ 64 <831000000>; > > + opp-hz-real = /bits/ 64 <831000000>, > > + /bits/ 64 <831000000>; > > + opp-microvolt = <781250>, > > + <781250>; > > + }; > > + > > + opp-855000000 { > > + opp-hz = /bits/ 64 <855000000>; > > + opp-hz-real = /bits/ 64 <855000000>, > > + /bits/ 64 <855000000>; > > + opp-microvolt = <793750>, > > + <793750>; > > + }; > > + > > + opp-902000000 { > > + opp-hz = /bits/ 64 <902000000>; > > + opp-hz-real = /bits/ 64 <902000000>, > > + /bits/ 64 <902000000>; > > + opp-microvolt = <818750>, > > + <818750>; > > + }; > > + > > + opp-950000000 { > > + opp-hz = /bits/ 64 <950000000>; > > + opp-hz-real = /bits/ 64 <950000000>, > > + /bits/ 64 <950000000>; > > + opp-microvolt = <843750>, > > + <843750>; > > + }; > > + }; > > + > > mfgcfg: syscon@13fbf000 { > > compatible = "mediatek,mt8192-mfgcfg", "syscon"; > > reg = <0 0x13fbf000 0 0x1000>; > > > _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
