On Wed, 2020-12-23 at 21:35 +0100, Stefan Wahren wrote: > From: Phil Elwell <phil@xxxxxxxxxxxxxxx> > > MMU exception conditions are reported in the V3D_MMU_CTRL register as > write-1-to-clear (W1C) bits. The MMU interrupt handling code clears any > exceptions, but does so by masking out any other bits and writing the > result back. There are some important control bits in that register, > including MMU_ENABLE, so a safer approach is to simply write back the > value just read unaltered. > > Signed-off-by: Phil Elwell <phil@xxxxxxxxxxxxxxx> > Signed-off-by: Stefan Wahren <stefan.wahren@xxxxxxxx> > --- Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@xxxxxxx> Regards, Nicolas
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