22.12.2020 03:14, Rob Herring пишет: > On Thu, Dec 17, 2020 at 09:05:56PM +0300, Dmitry Osipenko wrote: >> Document "clocks" sub-node which describes Tegra SoC clocks that require >> a higher voltage of the core power domain in order to operate properly on >> a higher rates. > > Seems like an odd reason to have a bunch of child nodes. It very much > seems like a problem you'd need to solve after you design the binding > which should be fixed within the kernel. The reason is that multiple root SoC PLL clocks need to have individual OPP table because proper voltage should be maintained for these clocks based on the clock rate. Some of the clocks do not belong to any specific device and there is a need to specify the OPP table for them. Each child node represents an individual clock with the clock's OPP table and power domain. Some clocks belong to a specific device, but don't require high voltages and it's very convenient that clk device could manage voltage for these clocks, instead of populating each device with OPP support (PWM, MMC and etc). I'll update the commit message with a better explanation in v3. > This is also above my threshold for 'convert to schema' first... Alright, will convert it in v3. _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
