Hi Maxime
On Thu, 10 Dec 2020 at 13:47, Maxime Ripard <maxime@xxxxxxxxxx> wrote:
>
> The CEC clock divider needs to output a frequency of 40kHz from the HSM
> rate on the BCM2835. The driver used to have a fixed frequency for it,
> but that changed and we now need to compute it dynamically to maintain
> the proper rate.
>
> Fixes: cd4cb49dc5bb ("drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate")
> Signed-off-by: Maxime Ripard <maxime@xxxxxxxxxx>
Reviewed-by: Dave Stevenson <dave.stevenson@xxxxxxxxxxxxxxx>
(To be a total pedant it's still a fixed frequency on vc4, but it's
configurable via the variant entry).
> ---
> drivers/gpu/drm/vc4/vc4_hdmi.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
> index eff3bac562c6..0c53d7427d15 100644
> --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
> +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
> @@ -1586,6 +1586,7 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
> {
> struct cec_connector_info conn_info;
> struct platform_device *pdev = vc4_hdmi->pdev;
> + u16 clk_cnt;
> u32 value;
> int ret;
>
> @@ -1611,8 +1612,9 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
> * divider: the hsm_clock rate and this divider setting will
> * give a 40 kHz CEC clock.
> */
> + clk_cnt = clk_get_rate(vc4_hdmi->hsm_clock) / CEC_CLOCK_FREQ;
> value |= VC4_HDMI_CEC_ADDR_MASK |
> - (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
> + (clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
> HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
> ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
> vc4_cec_irq_handler,
> --
> 2.28.0
>
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