Hi Maxime
On Mon, 7 Dec 2020 at 15:57, Maxime Ripard <maxime@xxxxxxxxxx> wrote:
>
> Unlike the previous generations, the HSM clock limitation is way above
> what we can reach without scrambling, so let's move the maximum
> frequency we support to the maximum clock frequency without scrambling.
>
> Signed-off-by: Maxime Ripard <maxime@xxxxxxxxxx>
Reviewed-by: Dave Stevenson <dave.stevenson@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/vc4/vc4_hdmi.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
> index 5310e06efc82..f4ff6b5db484 100644
> --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
> +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
> @@ -82,6 +82,8 @@
> #define CEC_CLOCK_FREQ 40000
> #define VC4_HSM_MID_CLOCK 149985000
>
> +#define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
> +
> static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
> {
> struct drm_info_node *node = (struct drm_info_node *)m->private;
> @@ -1911,7 +1913,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
> .encoder_type = VC4_ENCODER_TYPE_HDMI0,
> .debugfs_name = "hdmi0_regs",
> .card_name = "vc4-hdmi-0",
> - .max_pixel_clock = 297000000,
> + .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
> .registers = vc5_hdmi_hdmi0_fields,
> .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
> .phy_lane_mapping = {
> @@ -1937,7 +1939,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
> .encoder_type = VC4_ENCODER_TYPE_HDMI1,
> .debugfs_name = "hdmi1_regs",
> .card_name = "vc4-hdmi-1",
> - .max_pixel_clock = 297000000,
> + .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
> .registers = vc5_hdmi_hdmi1_fields,
> .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
> .phy_lane_mapping = {
> --
> 2.28.0
>
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