> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@xxxxxxxxx>
> Sent: Sunday, November 1, 2020 3:37 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx; Shankar, Uma <uma.shankar@xxxxxxxxx>;
> Kulkarni, Vandita <vandita.kulkarni@xxxxxxxxx>; ville.syrjala@xxxxxxxxxxxxxxx;
> Sharma, Swati2 <swati2.sharma@xxxxxxxxx>
> Subject: [PATCH v2 07/13] drm/i915: Capture max frl rate for PCON in dfp cap
> structure
>
> HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON and by the
> sink.
>
> This patch captures these in dfp cap structure in intel_dp and uses these to
> prune connector modes that cannot be supported by the PCON and sink FRL
> bandwidth.
>
> v2: Addressed review comments from Uma Shankar:
> -tweaked the comparison of target bw and pcon frl bw to avoid roundup errors.
> -minor modification of field names and comments.
Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx>
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 38 ++++++++++++++++++-
> 2 files changed, 37 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f6f0626649e0..282c6ee76384 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1397,6 +1397,7 @@ struct intel_dp {
> struct {
> int min_tmds_clock, max_tmds_clock;
> int max_dotclock;
> + int pcon_max_frl_bw, sink_max_frl_bw;
> u8 max_bpc;
> bool ycbcr_444_to_420;
> } dfp;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 818daab252f3..caf7666f1892 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -684,6 +684,29 @@ intel_dp_mode_valid_downstream(struct
> intel_connector *connector,
> const struct drm_display_info *info = &connector->base.display_info;
> int tmds_clock;
>
> + /*
> + * If PCON and HDMI2.1 sink both support FRL MODE, check FRL
> + * bandwidth constraints.
> + */
> + if (intel_dp->dfp.pcon_max_frl_bw) {
> + int target_bw;
> + int max_frl_bw;
> + int bpp = intel_dp_mode_min_output_bpp(&connector->base,
> mode);
> +
> + target_bw = bpp * target_clock;
> +
> + max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw,
> + intel_dp->dfp.sink_max_frl_bw);
> +
> + /* converting bw from Gbps to Kbps*/
> + max_frl_bw = max_frl_bw * 1000000;
> +
> + if (target_bw > max_frl_bw)
> + return MODE_CLOCK_HIGH;
> +
> + return MODE_OK;
> + }
> +
> if (intel_dp->dfp.max_dotclock &&
> target_clock > intel_dp->dfp.max_dotclock)
> return MODE_CLOCK_HIGH;
> @@ -6366,13 +6389,21 @@ intel_dp_update_dfp(struct intel_dp *intel_dp,
> intel_dp->downstream_ports,
> edid);
>
> + intel_dp->dfp.pcon_max_frl_bw =
> + drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
> + intel_dp->downstream_ports);
> +
> + intel_dp->dfp.sink_max_frl_bw =
> +drm_dp_get_hdmi_sink_max_frl_bw(&intel_dp->aux);
> +
> drm_dbg_kms(&i915->drm,
> - "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d,
> TMDS clock %d-%d\n",
> + "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d,
> TMDS clock
> +%d-%d, PCON Max FRL BW %dGbps, Sink Max FRL BW %dGbps\n",
> connector->base.base.id, connector->base.name,
> intel_dp->dfp.max_bpc,
> intel_dp->dfp.max_dotclock,
> intel_dp->dfp.min_tmds_clock,
> - intel_dp->dfp.max_tmds_clock);
> + intel_dp->dfp.max_tmds_clock,
> + intel_dp->dfp.pcon_max_frl_bw,
> + intel_dp->dfp.sink_max_frl_bw);
> }
>
> static void
> @@ -6464,6 +6495,9 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
> intel_dp->dfp.min_tmds_clock = 0;
> intel_dp->dfp.max_tmds_clock = 0;
>
> + intel_dp->dfp.pcon_max_frl_bw = 0;
> + intel_dp->dfp.sink_max_frl_bw = 0;
> +
> intel_dp->dfp.ycbcr_444_to_420 = false;
> connector->base.ycbcr_420_allowed = false; }
> --
> 2.17.1
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