Re: [PATCH v3 00/56] Convert DSI code to use drm_mipi_dsi and drm_panel

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Hi Tomi,
I hope you had a good weekend.

And I have added back the CC: list because I think we have progress after our internal discussion and only one issue remaining.

> Am 13.11.2020 um 15:49 schrieb Tomi Valkeinen <tomi.valkeinen@xxxxxx>:
> 
> On 13/11/2020 16:41, H. Nikolaus Schaller wrote:
>> Hi Tomi,
>> 
>>> Am 13.11.2020 um 14:38 schrieb Tomi Valkeinen <tomi.valkeinen@xxxxxx>:
>>> 
>>> On 13/11/2020 15:35, H. Nikolaus Schaller wrote:
>>> 
>>>> So I'd say dsi_vc_send_short() fails if dsi_vc_enable_hs(0, 0) and not dsi_vc_enable_hs(0, 1)
>>> 
>>> Oh, forgot to mention this: remove MIPI_DSI_MODE_LPM from the panel driver.
>> 
>> Yes! This makes sending the init sequence work.
>> 
>> I just have failures from w677l_read() but that may be the panel driver wrapper code.
> 
> Ok, great! It would be good to have reads working too.

I have fixed it. The call to mipi_dsi_dcs_read() was wrong.

> That way we can know for sure if the commands
> go back and forth correctly (e.g. verify the panel version ID).

I can now read registers. Panel version ID is nonsense but I know that it was before.
Maybe they did not flash it during production since I only read 0x40,0x00,0x00.
But we can read it.

> 
>> If I remove all read commands (they are not necessary for operation), there are no error
>> messages and everything succeeds. I have a /dev/fb0.
>> 
>> But I have no picture yet.
>> 
>> Initially I thought that it was just the missing code to handle an external PWM backlight.
>> But even with (and backlight working), I have just a framebuffer with black screen.
>> 
>> Anyways, I think we are very close. And this is a great step forwards so that I need a
>> break...
>> 
>> Maybe I manage to consolidate the panel driver code before v5.10-rc4 arrives. This
>> would give a freshly merged letux tree.
> 
> Usually backlight glow is visible even if there's no picture.

Well, it did not turn the PWM on at all. Now this works as well.

Still I have no picture. But the readout of the register 0x45 (scan line) shows varying
values. Therefore I think the vsync is running and incrementing the scan line counter.

> But a comparison between the old, working driver, with dsi debugs enabled, may give some hints. A
> DISPC & DSI reg dump for both cases may also give hints.

I have a script to mount debugfs and dump registers. Results are attached.

Significant difference seem to be in:

DISPC_TIMING_H(LCD)
DSI_CLK_CTRL
DSI_VM_TIMING1
DSI_VM_TIMING6
DSI_VC_CTRL(0)
DSI_VC_CTRL(1)
DSI_DSIPHY_CFG2

The consolidated panel driver code is here:

	https://git.goldelico.com/?p=letux-kernel.git;a=shortlog;h=refs/heads/letux/boe-w677-dsi-panel-v2

Well, not yet clean for upstreaming but functionally much better than before.

What I have hacked is to mask out MIPI_DSI_MODE_LPM in mipi_dsi_attach(). This
can/will be replaced if your series can handle it.

BR,
Nikolaus

root@letux:~# ./debugdsi 
- DSS -
FCK = 192000000
- DISPC -
dispc fclk source = FCK
fck             192000000       
- DISPC-CORE-CLK -
lck             192000000       lck div 1
- LCD -
LCD clk source = PLL1:1
lck             153600000       lck div 1
pck             76800000        pck div 2
- LCD2 -
LCD2 clk source = FCK
lck             48000000        lck div 4
pck             48000000        pck div 1
- LCD3 -
LCD3 clk source = FCK
lck             48000000        lck div 4
pck             48000000        pck div 1
DISPC_REVISION                                     00000051
DISPC_SYSCONFIG                                    00002015
DISPC_SYSSTATUS                                    00000001
DISPC_IRQSTATUS                                    000000a2
DISPC_IRQENABLE                                    0812d640
DISPC_CONTROL                                      00018309
DISPC_CONFIG                                       0000020c
DISPC_CAPABLE                                      00000000
DISPC_LINE_STATUS                                  000003e3
DISPC_LINE_NUMBER                                  00000000
DISPC_GLOBAL_ALPHA                                 ffffffff
DISPC_CONTROL2                                     00000000
DISPC_CONFIG2                                      00000000
DISPC_CONTROL3                                     00000000
DISPC_CONFIG3                                      00000000
DISPC_GLOBAL_MFLAG_ATTRIBUTE                       00000001
DISPC_DEFAULT_COLOR(LCD)                           00000000
DISPC_TRANS_COLOR(LCD)                             00000000
DISPC_SIZE_MGR(LCD)                                04ff02cf
DISPC_TIMING_H(LCD)                                0040a100
DISPC_TIMING_V(LCD)                                0320323b
DISPC_POL_FREQ(LCD)                                00060000
DISPC_DIVISORo(LCD)                                00010002
DISPC_DATA_CYCLE1(LCD)                             00000000
DISPC_DATA_CYCLE2(LCD)                             00000000
DISPC_DATA_CYCLE3(LCD)                             00000000
DISPC_CPR_COEF_R(LCD)                              00000000
DISPC_CPR_COEF_G(LCD)                              00000000
DISPC_CPR_COEF_B(LCD)                              00000000
DISPC_DEFAULT_COLOR(TV)                            00000000
DISPC_TRANS_COLOR(TV)                              00000000
DISPC_SIZE_MGR(TV)                                 00000000
DISPC_DEFAULT_COLOR(LCD2)                          00000000
DISPC_TRANS_COLOR(LCD2)                            00000000
DISPC_SIZE_MGR(LCD2)                               00000000
DISPC_TIMING_H(LCD2)                               00000000
DISPC_TIMING_V(LCD2)                               00000000
DISPC_POL_FREQ(LCD2)                               00000000
DISPC_DIVISORo(LCD2)                               00040001
DISPC_DATA_CYCLE1(LCD2)                            00000000
DISPC_DATA_CYCLE2(LCD2)                            00000000
DISPC_DATA_CYCLE3(LCD2)                            00000000
DISPC_CPR_COEF_R(LCD2)                             00000000
DISPC_CPR_COEF_G(LCD2)                             00000000
DISPC_CPR_COEF_B(LCD2)                             00000000
DISPC_DEFAULT_COLOR(LCD3)                          00000000
DISPC_TRANS_COLOR(LCD3)                            00000000
DISPC_SIZE_MGR(LCD3)                               00000000
DISPC_TIMING_H(LCD3)                               00000000
DISPC_TIMING_V(LCD3)                               00000000
DISPC_POL_FREQ(LCD3)                               00000000
DISPC_DIVISORo(LCD3)                               00040001
DISPC_DATA_CYCLE1(LCD3)                            00000000
DISPC_DATA_CYCLE2(LCD3)                            00000000
DISPC_DATA_CYCLE3(LCD3)                            00000000
DISPC_CPR_COEF_R(LCD3)                             00000000
DISPC_CPR_COEF_G(LCD3)                             00000000
DISPC_CPR_COEF_B(LCD3)                             00000000
DISPC_OVL_BA0(GFX)                                 10100000
DISPC_OVL_BA1(GFX)                                 10100000
DISPC_OVL_POSITION(GFX)                            00000000
DISPC_OVL_SIZE(GFX)                                04ff02cf
DISPC_OVL_ATTRIBUTES(GFX)                          320040b1
DISPC_OVL_FIFO_THRESHOLD(GFX)                      07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(GFX)                    00000500
DISPC_OVL_ROW_INC(GFX)                             000074c1
DISPC_OVL_PIXEL_INC(GFX)                           00000001
DISPC_OVL_PRELOAD(GFX)                             000007ff
DISPC_OVL_MFLAG_THRESHOLD(GFX)                     05000400
DISPC_OVL_WINDOW_SKIP(GFX)                         00000000
DISPC_OVL_TABLE_BA(GFX)                            00000000
DISPC_OVL_BA0(VID1)                                00000000
DISPC_OVL_BA1(VID1)                                00000000
DISPC_OVL_POSITION(VID1)                           00000000
DISPC_OVL_SIZE(VID1)                               00000000
DISPC_OVL_ATTRIBUTES(VID1)                         02808400
DISPC_OVL_FIFO_THRESHOLD(VID1)                     07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(VID1)                   00000800
DISPC_OVL_ROW_INC(VID1)                            00000001
DISPC_OVL_PIXEL_INC(VID1)                          00000001
DISPC_OVL_PRELOAD(VID1)                            000007ff
DISPC_OVL_MFLAG_THRESHOLD(VID1)                    05000400
DISPC_OVL_FIR(VID1)                                04000400
DISPC_OVL_PICTURE_SIZE(VID1)                       00000000
DISPC_OVL_ACCU0(VID1)                              00000000
DISPC_OVL_ACCU1(VID1)                              00000000
DISPC_OVL_BA0_UV(VID1)                             00000000
DISPC_OVL_BA1_UV(VID1)                             00000000
DISPC_OVL_FIR2(VID1)                               04000400
DISPC_OVL_ACCU2_0(VID1)                            00000000
DISPC_OVL_ACCU2_1(VID1)                            00000000
DISPC_OVL_ATTRIBUTES2(VID1)                        00000000
DISPC_OVL_BA0(VID2)                                00000000
DISPC_OVL_BA1(VID2)                                00000000
DISPC_OVL_POSITION(VID2)                           00000000
DISPC_OVL_SIZE(VID2)                               00000000
DISPC_OVL_ATTRIBUTES(VID2)                         02808400
DISPC_OVL_FIFO_THRESHOLD(VID2)                     07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(VID2)                   00000800
DISPC_OVL_ROW_INC(VID2)                            00000001
DISPC_OVL_PIXEL_INC(VID2)                          00000001
DISPC_OVL_PRELOAD(VID2)                            000007ff
DISPC_OVL_MFLAG_THRESHOLD(VID2)                    05000400
DISPC_OVL_FIR(VID2)                                04000400
DISPC_OVL_PICTURE_SIZE(VID2)                       00000000
DISPC_OVL_ACCU0(VID2)                              00000000
DISPC_OVL_ACCU1(VID2)                              00000000
DISPC_OVL_BA0_UV(VID2)                             00000000
DISPC_OVL_BA1_UV(VID2)                             00000000
DISPC_OVL_FIR2(VID2)                               04000400
DISPC_OVL_ACCU2_0(VID2)                            00000000
DISPC_OVL_ACCU2_1(VID2)                            00000000
DISPC_OVL_ATTRIBUTES2(VID2)                        00000000
DISPC_OVL_BA0(VID3)                                00000000
DISPC_OVL_BA1(VID3)                                00000000
DISPC_OVL_POSITION(VID3)                           00000000
DISPC_OVL_SIZE(VID3)                               00000000
DISPC_OVL_ATTRIBUTES(VID3)                         02808400
DISPC_OVL_FIFO_THRESHOLD(VID3)                     07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(VID3)                   00000800
DISPC_OVL_ROW_INC(VID3)                            00000001
DISPC_OVL_PIXEL_INC(VID3)                          00000001
DISPC_OVL_PRELOAD(VID3)                            000007ff
DISPC_OVL_MFLAG_THRESHOLD(VID3)                    05000400
DISPC_OVL_FIR(VID3)                                04000400
DISPC_OVL_PICTURE_SIZE(VID3)                       00000000
DISPC_OVL_ACCU0(VID3)                              00000000
DISPC_OVL_ACCU1(VID3)                              00000000
DISPC_OVL_BA0_UV(VID3)                             00000000
DISPC_OVL_BA1_UV(VID3)                             00000000
DISPC_OVL_FIR2(VID3)                               04000400
DISPC_OVL_ACCU2_0(VID3)                            00000000
DISPC_OVL_ACCU2_1(VID3)                            00000000
DISPC_OVL_ATTRIBUTES2(VID3)                        00000000
DISPC_OVL_BA0(WB)                                  00000000
DISPC_OVL_BA1(WB)                                  00000000
DISPC_OVL_SIZE(WB)                                 00000000
DISPC_OVL_ATTRIBUTES(WB)                           00808000
DISPC_OVL_FIFO_THRESHOLD(WB)                       00080000
DISPC_OVL_FIFO_SIZE_STATUS(WB)                     00000800
DISPC_OVL_ROW_INC(WB)                              00000001
DISPC_OVL_PIXEL_INC(WB)                            00000001
DISPC_OVL_MFLAG_THRESHOLD(WB)                      03200280
DISPC_OVL_FIR(WB)                                  04000400
DISPC_OVL_PICTURE_SIZE(WB)                         00000000
DISPC_OVL_ACCU0(WB)                                00000000
DISPC_OVL_ACCU1(WB)                                00000000
DISPC_OVL_BA0_UV(WB)                               00000000
DISPC_OVL_BA1_UV(WB)                               00000000
DISPC_OVL_FIR2(WB)                                 04000400
DISPC_OVL_ACCU2_0(WB)                              00000000
DISPC_OVL_ACCU2_1(WB)                              00000000
DISPC_OVL_ATTRIBUTES2(WB)                          00000000
DISPC_OVL_FIR_COEF_H_0(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_1(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_2(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_3(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_4(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_5(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_6(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_7(VID1)                       00000000
DISPC_OVL_FIR_COEF_HV_0(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_1(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_2(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_3(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_4(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_5(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_6(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_7(VID1)                      00000000
DISPC_OVL_CONV_COEF_0(VID1)                        0199012a
DISPC_OVL_CONV_COEF_1(VID1)                        012a0000
DISPC_OVL_CONV_COEF_2(VID1)                        079c0730
DISPC_OVL_CONV_COEF_3(VID1)                        0000012a
DISPC_OVL_CONV_COEF_4(VID1)                        00000204
DISPC_OVL_FIR_COEF_V_0(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_1(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_2(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_3(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_4(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_5(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_6(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_7(VID1)                       00000000
DISPC_OVL_FIR_COEF_H2_0(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_1(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_2(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_3(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_4(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_5(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_6(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_7(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV2_0(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_1(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_2(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_3(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_4(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_5(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_6(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_7(VID1)                     00000000
DISPC_OVL_FIR_COEF_V2_0(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_1(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_2(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_3(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_4(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_5(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_6(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_7(VID1)                      00000000
DISPC_OVL_FIR_COEF_H_0(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_1(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_2(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_3(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_4(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_5(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_6(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_7(VID2)                       00000000
DISPC_OVL_FIR_COEF_HV_0(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_1(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_2(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_3(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_4(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_5(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_6(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_7(VID2)                      00000000
DISPC_OVL_CONV_COEF_0(VID2)                        0199012a
DISPC_OVL_CONV_COEF_1(VID2)                        012a0000
DISPC_OVL_CONV_COEF_2(VID2)                        079c0730
DISPC_OVL_CONV_COEF_3(VID2)                        0000012a
DISPC_OVL_CONV_COEF_4(VID2)                        00000204
DISPC_OVL_FIR_COEF_V_0(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_1(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_2(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_3(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_4(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_5(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_6(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_7(VID2)                       00000000
DISPC_OVL_FIR_COEF_H2_0(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_1(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_2(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_3(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_4(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_5(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_6(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_7(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV2_0(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_1(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_2(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_3(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_4(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_5(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_6(VID2)                     00000000
[  117.525871] DSI: dsi_runtime_get
[  117.532527] DSI: dsi_runtime_put
DISPC_OVL_FIR_COEF_HV2_7(VID2)                     00000000
DISPC_OVL_FIR_COEF_V2_0(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_1(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_2(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_3(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_4(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_5(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_6(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_7(VID2)                      00000000
DISPC_OVL_FIR_COEF_H_0(VID3)                       00000000
DISPC_OVL_FIR_COEF_H_1(VID3)                       00000000
DISPC_OVL_FIR_COEF_H_2(VID3)                       00000000
DISPC_OVL_FIR_COEF_H_3(VID3)                       00000000
DISPC_OVL_FIR_COEF_H_4(VID3)                       00000000
DISPC_OVL_FIR_COEF_H_5(VID3)                       00000000
DISPC_OVL_FIR_COEF_H_6(VID3)                       00000000
DISPC_OVL_FIR_COEF_H_7(VID3)                       00000000
DISPC_OVL_FIR_COEF_HV_0(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV_1(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV_2(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV_3(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV_4(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV_5(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV_6(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV_7(VID3)                      00000000
DISPC_OVL_CONV_COEF_0(VID3)                        0199012a
DISPC_OVL_CONV_COEF_1(VID3)                        012a0000
DISPC_OVL_CONV_COEF_2(VID3)                        079c0730
DISPC_OVL_CONV_COEF_3(VID3)                        0000012a
DISPC_OVL_CONV_COEF_4(VID3)                        00000204
DISPC_OVL_FIR_COEF_V_0(VID3)                       00000000
DISPC_OVL_FIR_COEF_V_1(VID3)                       00000000
DISPC_OVL_FIR_COEF_V_2(VID3)                       00000000
DISPC_OVL_FIR_COEF_V_3(VID3)                       00000000
DISPC_OVL_FIR_COEF_V_4(VID3)                       00000000
DISPC_OVL_FIR_COEF_V_5(VID3)                       00000000
DISPC_OVL_FIR_COEF_V_6(VID3)                       00000000
DISPC_OVL_FIR_COEF_V_7(VID3)                       00000000
DISPC_OVL_FIR_COEF_H2_0(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_1(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_2(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_3(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_4(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_5(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_6(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_7(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV2_0(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_1(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_2(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_3(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_4(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_5(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_6(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_7(VID3)                     00000000
DISPC_OVL_FIR_COEF_V2_0(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_1(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_2(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_3(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_4(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_5(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_6(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_7(VID3)                      00000000
cat: /sys/kernel/debug/omapdss/dsi1_irqs: No such file or directory
DSI_REVISION                        00000040
DSI_SYSCONFIG                       00000015
DSI_SYSSTATUS                       00000001
DSI_IRQSTATUS                       00000000
DSI_IRQENABLE                       0015c000
DSI_CTRL                            00eaee9f
DSI_COMPLEXIO_CFG1                  2a0dcba9
DSI_COMPLEXIO_IRQ_STATUS            00000000
DSI_COMPLEXIO_IRQ_ENABLE            3ff07fff
DSI_CLK_CTRL                        a030400b
DSI_TIMING1                         ffff1000
DSI_TIMING2                         ffffffff
DSI_VM_TIMING1                      00078003
DSI_VM_TIMING2                      043c3232
DSI_VM_TIMING3                      029a0500
DSI_CLK_TIMING                      00001b10
DSI_TX_FIFO_VC_SIZE                 13121110
DSI_RX_FIFO_VC_SIZE                 13121110
DSI_COMPLEXIO_CFG2                  00030000
DSI_RX_FIFO_VC_FULLNESS             00000000
DSI_VM_TIMING4                      00000000
DSI_TX_FIFO_VC_EMPTINESS            1f1f1e1f
DSI_VM_TIMING5                      00000000
DSI_VM_TIMING6                      01000007
DSI_VM_TIMING7                      00100010
DSI_STOPCLK_TIMING                  00000080
DSI_VC_CTRL(0)                      20808f81
DSI_VC_TE(0)                        00000000
DSI_VC_LONG_PACKET_HEADER(0)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(0)       00000000
DSI_VC_SHORT_PACKET_HEADER(0)       00000000
DSI_VC_IRQSTATUS(0)                 00000000
DSI_VC_IRQENABLE(0)                 000000db
DSI_VC_CTRL(1)                      20808fb1
DSI_VC_TE(1)                        00000000
DSI_VC_LONG_PACKET_HEADER(1)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(1)       00000000
DSI_VC_SHORT_PACKET_HEADER(1)       00000000
DSI_VC_IRQSTATUS(1)                 00000000
DSI_VC_IRQENABLE(1)                 000000db
DSI_VC_CTRL(2)                      20808d81
DSI_VC_TE(2)                        00000000
DSI_VC_LONG_PACKET_HEADER(2)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(2)       00000000
DSI_VC_SHORT_PACKET_HEADER(2)       00000000
DSI_VC_IRQSTATUS(2)                 00000000
DSI_VC_IRQENABLE(2)                 000000db
DSI_VC_CTRL(3)                      20808d81
DSI_VC_TE(3)                        00000000
DSI_VC_LONG_PACKET_HEADER(3)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(3)       00000000
DSI_VC_SHORT_PACKET_HEADER(3)       00000000
DSI_VC_IRQSTATUS(3)                 00000000
DSI_VC_IRQENABLE(3)                 000000db
DSI_DSIPHY_CFG0                     132b1322
DSI_DSIPHY_CFG1                     42c6103c
DSI_DSIPHY_CFG2                     b83e000f
DSI_DSIPHY_CFG5                     ff000000
DSI_PLL_CONTROL                     00000018
DSI_PLL_STATUS                      00006383
DSI_PLL_GO                          00000000
DSI_PLL_CONFIGURATION1              10a03000
DSI_PLL_CONFIGURATION2              00656004
root@letux:~# 
root@letux:~# ./debugdsi 
- DSS -
FCK = 192000000
- DISPC -
dispc fclk source = FCK
fck             192000000       
- DISPC-CORE-CLK -
lck             192000000       lck div 1
- LCD -
LCD clk source = PLL1:1
lck             153600000       lck div 1
pck             76800000        pck div 2
- LCD2 -
LCD2 clk source = FCK
lck             48000000        lck div 4
pck             48000000        pck div 1
- LCD3 -
LCD3 clk source = FCK
lck             48000000        lck div 4
pck             48000000        pck div 1
DISPC_REVISION                                     00000051
DISPC_SYSCONFIG                                    00002015
DISPC_SYSSTATUS                                    00000001
DISPC_IRQSTATUS                                    000000a2
DISPC_IRQENABLE                                    0812d640
DISPC_CONTROL                                      00018309
DISPC_CONFIG                                       0000020c
DISPC_CAPABLE                                      00000000
DISPC_LINE_STATUS                                  000001af
DISPC_LINE_NUMBER                                  00000000
DISPC_GLOBAL_ALPHA                                 ffffffff
DISPC_CONTROL2                                     00000000
DISPC_CONFIG2                                      00000000
DISPC_CONTROL3                                     00000000
DISPC_CONFIG3                                      00000000
DISPC_GLOBAL_MFLAG_ATTRIBUTE                       00000001
DISPC_DEFAULT_COLOR(LCD)                           00000000
DISPC_TRANS_COLOR(LCD)                             00000000
DISPC_SIZE_MGR(LCD)                                04ff02cf
DISPC_TIMING_H(LCD)                                09d00800
DISPC_TIMING_V(LCD)                                0320323b
DISPC_POL_FREQ(LCD)                                00060000
DISPC_DIVISORo(LCD)                                00010002
DISPC_DATA_CYCLE1(LCD)                             00000000
DISPC_DATA_CYCLE2(LCD)                             00000000
DISPC_DATA_CYCLE3(LCD)                             00000000
DISPC_CPR_COEF_R(LCD)                              00000000
DISPC_CPR_COEF_G(LCD)                              00000000
DISPC_CPR_COEF_B(LCD)                              00000000
DISPC_DEFAULT_COLOR(TV)                            00000000
DISPC_TRANS_COLOR(TV)                              00000000
DISPC_SIZE_MGR(TV)                                 00000000
DISPC_DEFAULT_COLOR(LCD2)                          00000000
DISPC_TRANS_COLOR(LCD2)                            00000000
DISPC_SIZE_MGR(LCD2)                               00000000
DISPC_TIMING_H(LCD2)                               00000000
DISPC_TIMING_V(LCD2)                               00000000
DISPC_POL_FREQ(LCD2)                               00000000
DISPC_DIVISORo(LCD2)                               00040001
DISPC_DATA_CYCLE1(LCD2)                            00000000
DISPC_DATA_CYCLE2(LCD2)                            00000000
DISPC_DATA_CYCLE3(LCD2)                            00000000
DISPC_CPR_COEF_R(LCD2)                             00000000
DISPC_CPR_COEF_G(LCD2)                             00000000
DISPC_CPR_COEF_B(LCD2)                             00000000
DISPC_DEFAULT_COLOR(LCD3)                          00000000
DISPC_TRANS_COLOR(LCD3)                            00000000
DISPC_SIZE_MGR(LCD3)                               00000000
DISPC_TIMING_H(LCD3)                               00000000
DISPC_TIMING_V(LCD3)                               00000000
DISPC_POL_FREQ(LCD3)                               00000000
DISPC_DIVISORo(LCD3)                               00040001
DISPC_DATA_CYCLE1(LCD3)                            00000000
DISPC_DATA_CYCLE2(LCD3)                            00000000
DISPC_DATA_CYCLE3(LCD3)                            00000000
DISPC_CPR_COEF_R(LCD3)                             00000000
DISPC_CPR_COEF_G(LCD3)                             00000000
DISPC_CPR_COEF_B(LCD3)                             00000000
DISPC_OVL_BA0(GFX)                                 d0003440
DISPC_OVL_BA1(GFX)                                 d0003440
DISPC_OVL_POSITION(GFX)                            00000000
DISPC_OVL_SIZE(GFX)                                04ff02cf
DISPC_OVL_ATTRIBUTES(GFX)                          320040b1
DISPC_OVL_FIFO_THRESHOLD(GFX)                      07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(GFX)                    00000500
DISPC_OVL_ROW_INC(GFX)                             000034c1
DISPC_OVL_PIXEL_INC(GFX)                           00000001
DISPC_OVL_PRELOAD(GFX)                             000007ff
DISPC_OVL_MFLAG_THRESHOLD(GFX)                     05000400
DISPC_OVL_WINDOW_SKIP(GFX)                         00000000
DISPC_OVL_TABLE_BA(GFX)                            00000000
DISPC_OVL_BA0(VID1)                                00000000
DISPC_OVL_BA1(VID1)                                00000000
DISPC_OVL_POSITION(VID1)                           00000000
DISPC_OVL_SIZE(VID1)                               00000000
DISPC_OVL_ATTRIBUTES(VID1)                         02808400
DISPC_OVL_FIFO_THRESHOLD(VID1)                     07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(VID1)                   00000800
DISPC_OVL_ROW_INC(VID1)                            00000001
DISPC_OVL_PIXEL_INC(VID1)                          00000001
DISPC_OVL_PRELOAD(VID1)                            000007ff
DISPC_OVL_MFLAG_THRESHOLD(VID1)                    05000400
DISPC_OVL_FIR(VID1)                                04000400
DISPC_OVL_PICTURE_SIZE(VID1)                       00000000
DISPC_OVL_ACCU0(VID1)                              00000000
DISPC_OVL_ACCU1(VID1)                              00000000
DISPC_OVL_BA0_UV(VID1)                             00000000
DISPC_OVL_BA1_UV(VID1)                             00000000
DISPC_OVL_FIR2(VID1)                               04000400
DISPC_OVL_ACCU2_0(VID1)                            00000000
DISPC_OVL_ACCU2_1(VID1)                            00000000
DISPC_OVL_ATTRIBUTES2(VID1)                        00000000
DISPC_OVL_BA0(VID2)                                00000000
DISPC_OVL_BA1(VID2)                                00000000
DISPC_OVL_POSITION(VID2)                           00000000
DISPC_OVL_SIZE(VID2)                               00000000
DISPC_OVL_ATTRIBUTES(VID2)                         02808400
DISPC_OVL_FIFO_THRESHOLD(VID2)                     07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(VID2)                   00000800
DISPC_OVL_ROW_INC(VID2)                            00000001
DISPC_OVL_PIXEL_INC(VID2)                          00000001
DISPC_OVL_PRELOAD(VID2)                            000007ff
DISPC_OVL_MFLAG_THRESHOLD(VID2)                    05000400
DISPC_OVL_FIR(VID2)                                04000400
DISPC_OVL_PICTURE_SIZE(VID2)                       00000000
DISPC_OVL_ACCU0(VID2)                              00000000
DISPC_OVL_ACCU1(VID2)                              00000000
DISPC_OVL_BA0_UV(VID2)                             00000000
DISPC_OVL_BA1_UV(VID2)                             00000000
DISPC_OVL_FIR2(VID2)                               04000400
DISPC_OVL_ACCU2_0(VID2)                            00000000
DISPC_OVL_ACCU2_1(VID2)                            00000000
DISPC_OVL_ATTRIBUTES2(VID2)                        00000000
DISPC_OVL_BA0(VID3)                                00000000
DISPC_OVL_BA1(VID3)                                00000000
DISPC_OVL_POSITION(VID3)                           00000000
DISPC_OVL_SIZE(VID3)                               00000000
DISPC_OVL_ATTRIBUTES(VID3)                         02808400
DISPC_OVL_FIFO_THRESHOLD(VID3)                     07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(VID3)                   00000800
DISPC_OVL_ROW_INC(VID3)                            00000001
DISPC_OVL_PIXEL_INC(VID3)                          00000001
DISPC_OVL_PRELOAD(VID3)                            000007ff
DISPC_OVL_MFLAG_THRESHOLD(VID3)                    05000400
DISPC_OVL_FIR(VID3)                                04000400
DISPC_OVL_PICTURE_SIZE(VID3)                       00000000
DISPC_OVL_ACCU0(VID3)                              00000000
DISPC_OVL_ACCU1(VID3)                              00000000
DISPC_OVL_BA0_UV(VID3)                             00000000
DISPC_OVL_BA1_UV(VID3)                             00000000
DISPC_OVL_FIR2(VID3)                               04000400
DISPC_OVL_ACCU2_0(VID3)                            00000000
DISPC_OVL_ACCU2_1(VID3)                            00000000
DISPC_OVL_ATTRIBUTES2(VID3)                        00000000
DISPC_OVL_BA0(WB)                                  00000000
DISPC_OVL_BA1(WB)                                  00000000
DISPC_OVL_SIZE(WB)                                 00000000
DISPC_OVL_ATTRIBUTES(WB)                           00808000
DISPC_OVL_FIFO_THRESHOLD(WB)                       00080000
DISPC_OVL_FIFO_SIZE_STATUS(WB)                     00000800
DISPC_OVL_ROW_INC(WB)                              00000001
DISPC_OVL_PIXEL_INC(WB)                            00000001
DISPC_OVL_MFLAG_THRESHOLD(WB)                      03200280
DISPC_OVL_FIR(WB)                                  04000400
DISPC_OVL_PICTURE_SIZE(WB)                         00000000
DISPC_OVL_ACCU0(WB)                                00000000
DISPC_OVL_ACCU1(WB)                                00000000
DISPC_OVL_BA0_UV(WB)                               00000000
DISPC_OVL_BA1_UV(WB)                               00000000
DISPC_OVL_FIR2(WB)                                 04000400
DISPC_OVL_ACCU2_0(WB)                              00000000
DISPC_OVL_ACCU2_1(WB)                              00000000
DISPC_OVL_ATTRIBUTES2(WB)                          00000000
DISPC_OVL_FIR_COEF_H_0(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_1(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_2(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_3(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_4(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_5(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_6(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_7(VID1)                       00000000
DISPC_OVL_FIR_COEF_HV_0(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_1(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_2(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_3(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_4(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_5(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_6(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_7(VID1)                      00000000
DISPC_OVL_CONV_COEF_0(VID1)                        0199012a
DISPC_OVL_CONV_COEF_1(VID1)                        012a0000
DISPC_OVL_CONV_COEF_2(VID1)                        079c0730
DISPC_OVL_CONV_COEF_3(VID1)                        0000012a
DISPC_OVL_CONV_COEF_4(VID1)                        00000204
DISPC_OVL_FIR_COEF_V_0(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_1(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_2(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_3(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_4(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_5(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_6(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_7(VID1)                       00000000
DISPC_OVL_FIR_COEF_H2_0(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_1(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_2(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_3(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_4(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_5(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_6(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_7(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV2_0(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_1(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_2(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_3(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_4(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_5(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_6(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_7(VID1)                     00000000
DISPC_OVL_FIR_COEF_V2_0(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_1(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_2(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_3(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_4(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_5(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_6(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_7(VID1)                      00000000
DISPC_OVL_FIR_COEF_H_0(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_1(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_2(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_3(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_4(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_5(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_6(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_7(VID2)                       00000000
DISPC_OVL_FIR_COEF_HV_0(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_1(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_2(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_3(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_4(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_5(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_6(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_7(VID2)                      00000000
DISPC_OVL_CONV_COEF_0(VID2)                        0199012a
DISPC_OVL_CONV_COEF_1(VID2)                        012a0000
DISPC_OVL_CONV_COEF_2(VID2)                        079c0730
DISPC_OVL_CONV_COEF_3(VID2)                        0000012a
DISPC_OVL_CONV_COEF_4(VID2)                        00000204
DISPC_OVL_FIR_COEF_V_0(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_1(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_2(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_3(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_4(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_5(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_6(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_7(VID2)                       00000000
DISPC_OVL_FIR_COEF_H2_0(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_1(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_2(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_3(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_4(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_5(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_6(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_7(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV2_0(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_1(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_2(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_3(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_4(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_5(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_6(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_7(VID2)                     00000000
DISPC_OVL_FIR_COEF_V2_0(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_1(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_2(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_3(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_4(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_5(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_6(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_7(VID2)                      00000000
DISPC_OVL_FIR_COEF_H_0(VID3)                       00000000
DISPC_OVL_FIR_COEF_H_1(VID3)                       00000000
DISPC_OVL_FIR_COEF_H_2(VID3)                       00000000
DISPC_OVL_FIR_COEF_H_3(VID3)                       00000000
DISPC_OVL_FIR_COEF_H_4(VID3)                       00000000
DISPC_OVL_FIR_COEF_H_5(VID3)                       00000000
DISPC_OVL_FIR_COEF_H_6(VID3)                       00000000
DISPC_OVL_FIR_COEF_H_7(VID3)                       00000000
DISPC_OVL_FIR_COEF_HV_0(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV_1(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV_2(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV_3(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV_4(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV_5(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV_6(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV_7(VID3)                      00000000
DISPC_OVL_CONV_COEF_0(VID3)                        0199012a
DISPC_OVL_CONV_COEF_1(VID3)                        012a0000
DISPC_OVL_CONV_COEF_2(VID3)                        079c0730
DISPC_OVL_CONV_COEF_3(VID3)                        0000012a
DISPC_OVL_CONV_COEF_4(VID3)                        00000204
DISPC_OVL_FIR_COEF_V_0(VID3)                       00000000
DISPC_OVL_FIR_COEF_V_1(VID3)                       00000000
DISPC_OVL_FIR_COEF_V_2(VID3)                       00000000
DISPC_OVL_FIR_COEF_V_3(VID3)                       00000000
DISPC_OVL_FIR_COEF_V_4(VID3)                       00000000
DISPC_OVL_FIR_COEF_V_5(VID3)                       00000000
DISPC_OVL_FIR_COEF_V_6(VID3)                       00000000
DISPC_OVL_FIR_COEF_V_7(VID3)                       00000000
DISPC_OVL_FIR_COEF_H2_0(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_1(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_2(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_3(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_4(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_5(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_6(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_7(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV2_0(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_1(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_2(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_3(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_4(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_5(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_6(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_7(VID3)                     00000000
DISPC_OVL_FIR_COEF_V2_0(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_1(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_2(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_3(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_4(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_5(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_6(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_7(VID3)                      00000000
cat: /sys/kernel/debug/omapdss/dsi1_irqs: No such file or directory
DSI_REVISION                        00000040
DSI_SYSCONFIG                       00000015
DSI_SYSSTATUS                       00000001
DSI_IRQSTATUS                       00000000
DSI_IRQENABLE                       0015c000
DSI_CTRL                            00eaee9f
DSI_COMPLEXIO_CFG1                  2a0dcba9
DSI_COMPLEXIO_IRQ_STATUS            00000000
DSI_COMPLEXIO_IRQ_ENABLE            3ff07fff
DSI_CLK_CTRL                        a030600b
DSI_TIMING1                         ffff1000
DSI_TIMING2                         ffffffff
DSI_VM_TIMING1                      00005076
DSI_VM_TIMING2                      043c3232
DSI_VM_TIMING3                      029a0500
DSI_CLK_TIMING                      00001b10
DSI_TX_FIFO_VC_SIZE                 13121110
DSI_RX_FIFO_VC_SIZE                 13121110
DSI_COMPLEXIO_CFG2                  00030000
DSI_RX_FIFO_VC_FULLNESS             00000000
DSI_VM_TIMING4                      00000000
DSI_TX_FIFO_VC_EMPTINESS            1f1f1f1f
DSI_VM_TIMING5                      00000000
DSI_VM_TIMING6                      01340007
DSI_VM_TIMING7                      00100010
DSI_STOPCLK_TIMING                  00000080
DSI_VC_CTRL(0)                      20808f91
DSI_VC_TE(0)                        00000000
DSI_VC_LONG_PACKET_HEADER(0)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(0)       00000000
DSI_VC_SHORT_PACKET_HEADER(0)       00000000
DSI_VC_IRQSTATUS(0)                 00000004
DSI_VC_IRQENABLE(0)                 000000db
DSI_VC_CTRL(1)                      20808d81
DSI_VC_TE(1)                        00000000
DSI_VC_LONG_PACKET_HEADER(1)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(1)       00000000
DSI_VC_SHORT_PACKET_HEADER(1)       00000000
DSI_VC_IRQSTATUS(1)                 00000004
DSI_VC_IRQENABLE(1)                 000000db
DSI_VC_CTRL(2)                      20808d81
DSI_VC_TE(2)                        00000000
DSI_VC_LONG_PACKET_HEADER(2)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(2)       00000000
DSI_VC_SHORT_PACKET_HEADER(2)       00000000
DSI_VC_IRQSTATUS(2)                 00000000
DSI_VC_IRQENABLE(2)                 000000db
DSI_VC_CTRL(3)                      20808d81
DSI_VC_TE(3)                        00000000
DSI_VC_LONG_PACKET_HEADER(3)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(3)       00000000
DSI_VC_SHORT_PACKET_HEADER(3)       00000000
DSI_VC_IRQSTATUS(3)                 00000000
DSI_VC_IRQENABLE(3)                 000000db
DSI_DSIPHY_CFG0                     132b1322
DSI_DSIPHY_CFG1                     42c6103c
DSI_DSIPHY_CFG2                     b800000f
DSI_DSIPHY_CFG5                     ff000000
DSI_PLL_CONTROL                     00000018
DSI_PLL_STATUS                      00006383
DSI_PLL_GO                          00000000
DSI_PLL_CONFIGURATION1              10a03000
DSI_PLL_CONFIGURATION2              00656004
root@letux:~# 

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