20. 11. 11. 오후 12:04에 Inki Dae 이(가) 쓴 글: > > > 20. 11. 10. 오후 5:13에 Michael Tretter 이(가) 쓴 글: >> On Mon, 09 Nov 2020 12:15:39 +0900, Inki Dae wrote: >>> 20. 9. 11. 오후 10:53에 Michael Tretter 이(가) 쓴 글: >>>> This is v2 of the series to convert the Exynos MIPI DSI driver into a drm >>>> bridge and make it usable with other drivers. Although the driver is >>>> converted, it still supports the component framework API to stay compliant >>>> with the Exynos DRM driver. >>>> >>>> The Exynos MIPI DSI Phy is also found on the i.MX8M Mini. However, on the >>>> i.MX8M Mini, the bridge is driven by an LCDIF display controller instead of >>>> the Exynos Decon. The driver for the LCDIF does not use the component >>>> framework, but uses drm bridges. >>>> >>>> I don't have any Exynos SoC to actually test the series. I build a dummy to >>>> test the bridge with a component driver, to make sure that at least the >>>> initialization is working. Furthermore, tested the driver as a bridge with a >>>> few additional unfinished patches on the i.MX8M Mini EVK. However, somebody >>>> should verify that the driver is still working on Exynos hardware. >>>> >>>> I also changed the order of the patches to first make the driver more platform >>>> independent (patches 2 to 8), then convert to a drm bridge driver (patches 10 >>> >>> Just a fundamental question, A MIPI-DSI(Display Serial Interface) bus device >>> would be one of an encoder type of devices not bridge such as DSI to LVDS >>> and LVDS to DSI bridge devices, and also image enhancer and image compressor >>> in case of Exynos. >> >> I don't understand, why the MIPI-DSI bus device would be an encoder type and >> DSI to LVDS or MIPI-DSI to HDMI would be bridges. For example, the device tree >> documentation for the DSIM states that the DSIM receives RGB video as input >> and produces MIPI-DSI as output. Thus, the DSIM is basically a parallel RGB to > > MIPI-DSI receives RGB video as input and encodes it to MIPI packet and then transfers the packet to MIPI panel. > And finally, MIPI panel decodes the packet and updates it - RGB data - on its SRAM. > > MIPI-DSI driver programs how the RGB video should be made as MIPI packet. For more detail, you could refer to MIPI-DSI spec. > This would be why we handle MIPI-DSI driver as an encoder like other ARM SoC DRM drivers did. > >> MIPI-DSI bridge and the encoder is the LCD controller that encodes the video >> data as parallel RGB. >> >> On the i.MX8MM, the LCDIF is already the encoder. On Exynos, the series >> implements the encoder in the platform glue, but in the end the encoder can >> probably be moved to the DECON. > > As you know, Display controller can transfer RGB video to various devices such as RGB panel, CPU panel, LVDS panel via LVDS bridge, MIPI panel via MIPI-DSI bus device, and so on like below, > > Display Controller --> RGB panel or CPU panel. > Display Controller --> LVDS bridge --> LVDS panel. > Display Controller --> MIPI DSI bus device --> MIPI Panel. > ... > > Display controller drivers such as FIMD and DECON series in case of Exynos don't create an encoder driver-internally instead of it depends on Display pipeline configuration - what kind of Display panel is used. > In fact, if the Display pipeline uses RGB panel or CPU panel without Display bus device such as MIPI-DSI, then FIMD and DECON drivers create an encoder for it internally - just we separated the code to consider other type of panels. > > On the I.MX8MM, could you share how to handle an encoder if some board has only MIPI-DSI panel, and in this case, where is an encoder for it created? I looked into I.MX8MM DRM driver but didn't find MIPI-DSI driver. > Seems that they support only parallel display, HDMI and LVDS panel. One more thing, If I saw correctly, the LVDS driver of IMX DRM - lmx_ldb - creates an encoder internally like MIPI-DSI driver of Exynos DRM did. > > Thanks, > Inki Dae > >> >>> Why do you want to convert such MIPI-DSI driver to bridge type of driver? >>> Seems not sensible. The reason would be just to share MIPI-DSI phy driver >>> for Exynos with i.MX8M Mini? >> >> Yes, the reason is that the driver should be shared between Exynos and >> i.MX8MM. It is the same IP and I don't see a reason why we should introduce >> another driver for the same IP if the driver works for both SoCs. >> >> Michael >> > _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
