On Fri, 2020-10-16 at 12:04 -0500, Rob Herring wrote: > On Tue, Oct 13, 2020 at 04:52:01PM +0800, Chunfeng Yun wrote: > > Convert phy-mtk-tphy.txt to YAML schema mediatek,tphy.yaml > > > > Signed-off-by: Chunfeng Yun <chunfeng.yun@xxxxxxxxxxxx> > > --- > > v2: modify description and compatible > > --- > > .../bindings/phy/mediatek,tphy.yaml | 263 ++++++++++++++++++ > > .../devicetree/bindings/phy/phy-mtk-tphy.txt | 162 ----------- > > 2 files changed, 263 insertions(+), 162 deletions(-) > > create mode 100755 Documentation/devicetree/bindings/phy/mediatek,tphy.yaml > > delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml > > new file mode 100755 > > index 000000000000..56ad8be69095 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml > > @@ -0,0 +1,263 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +# Copyright (c) 2020 MediaTek > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek T-PHY Controller Device Tree Bindings > > + > > +maintainers: > > + - Chunfeng Yun <chunfeng.yun@xxxxxxxxxxxx> > > + > > +description: | > > + The T-PHY controller supports physical layer functionality for a number of > > + controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA. [...] > > +properties: > > + $nodename: > > + pattern: "^t-phy@[0-9a-f]+$" > > Wrong indentation. Should be 1 less. Yes, will fix it > > > + > > + compatible: > > + oneOf: > > + - items: > > + - enum: > > + - mediatek,mt2701-tphy > > + - mediatek,mt7623-tphy > > + - mediatek,mt7622-tphy > > + - mediatek,mt8516-tphy > > + - const: mediatek,generic-tphy-v1 > > + - items: > > + - enum: > > + - mediatek,mt2712-tphy > > + - mediatek,mt7629-tphy > > + - mediatek,mt8183-tphy > > + - const: mediatek,generic-tphy-v2 > > + - const: mediatek,mt2701-u3phy > > + deprecated: true > > + - const: mediatek,mt2712-u3phy > > + deprecated: true > > + - const: mediatek,mt8173-u3phy > > + > > + reg: > > + description: | > > Don't need '|' if there's no formatting to preserve. Got it > > > + Register shared by multiple ports, exclude port's private register. > > + It is needed for T-PHY V1, such as mt2701 and mt8173, but not for > > + T-PHY V2, such as mt2712. > > + maxItems: 1 > > + > > + "#address-cells": > > + enum: [1, 2] > > + > > + "#size-cells": > > + enum: [1, 2] > > Wrong indent. Will fix it and check it in other patches > > > + > > + # Used with non-empty value if optional 'reg' is not provided. > > + # The format of the value is an arbitrary number of triplets of > > + # (child-bus-address, parent-bus-address, length). > > + ranges: true > > + > > + mediatek,src-ref-clk-mhz: > > + description: > > + Frequency of reference clock for slew rate calibrate > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + default: 26 > > + > > + mediatek,src-coef: > > + description: > > + Coefficient for slew rate calibrate, depends on SoC process > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + default: 28 > > + > > +# Required child node: > > +patternProperties: > > + "^usb-phy@[0-9a-f]+$": > > + type: object > > + description: | > > + A sub-node is required for each port the controller provides. > > + Address range information including the usual 'reg' property > > + is used inside these nodes to describe the controller's topology. > > + > > + properties: > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + minItems: 1 > > + maxItems: 2 > > + items: > > + - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz) > > + - description: Reference clock of analog phy > > + description: | > > + Uses both clocks if the clock of analog and digital phys are > > + separated, otherwise uses "ref" clock only if needed. > > + > > + clock-names: > > + minItems: 1 > > + maxItems: 2 > > + items: > > + - const: ref > > + - const: da_ref > > + > > + "#phy-cells": > > + const: 1 > > + description: | > > + The cells contain the following arguments. > > + > > + - description: The PHY type > > + enum: > > + - PHY_TYPE_USB2 > > + - PHY_TYPE_USB3 > > + - PHY_TYPE_PCIE > > + - PHY_TYPE_SATA > > + > > + #The following optional vendor properties are only for debug or HQA test > > space ^ Ok, will add it > > > + mediatek,eye-src: > > + description: > > + The value of slew rate calibrate (U2 phy) > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 1 > > + maximum: 7 > > + > > + mediatek,eye-vrt: > > + description: > > + The selection of VRT reference voltage (U2 phy) > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 1 > > + maximum: 7 > > + > > + mediatek,eye-term: > > + description: > > + The selection of HS_TX TERM reference voltage (U2 phy) > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 1 > > + maximum: 7 > > + > > + mediatek,intr: > > + description: > > + The selection of internal resistor (U2 phy) > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 1 > > + maximum: 31 > > + > > + mediatek,discth: > > + description: > > + The selection of disconnect threshold (U2 phy) > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 1 > > + maximum: 15 > > + > > + mediatek,bc12: > > + description: > > + Specify the flag to enable BC1.2 if support it > > + type: boolean > > + > > + required: > > + - reg > > + - "#phy-cells" > > + > > + additionalProperties: false > > + > > +required: > > + - compatible > > + - "#address-cells" > > + - "#size-cells" > > + - ranges > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt8173-clk.h> > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/phy/phy.h> > > + susb: usb@11271000 { > > Drop unused labels. Ok > > > + compatible = "mediatek,mt8173-mtu3"; > > + reg = <0x11271000 0x3000>, <0x11280700 0x0100>; > > + reg-names = "mac", "ippc"; > > + phys = <&u2port0 PHY_TYPE_USB2>, > > + <&u3port0 PHY_TYPE_USB3>, > > + <&u2port1 PHY_TYPE_USB2>; > > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; > > + }; > > + > > + u3phy: t-phy@11290000 { > > + compatible = "mediatek,mt8173-u3phy"; > > + reg = <0x11290000 0x800>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > + status = "okay"; > > Don't show status in examples. Ok, will remove it Thanks a lot > > > + > > + u2port0: usb-phy@11290800 { > > + reg = <0x11290800 0x100>; > > + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>; > > + clock-names = "ref", "da_ref"; > > + #phy-cells = <1>; > > + status = "okay"; > > + }; [...] > > 2.18.0 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
