tree: git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next-vangogh
head: 6067a749d66ef3815908c86ee0b08733e391955f
commit: 356e0c5b8e5c7cd698641f3f7605d25ad793b159 [45/47] drm/amd/display: Add dcn3.01 support to DC
config: i386-randconfig-s031-20200925 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.2-201-g24bdaac6-dirty
git remote add radeon-alex git://people.freedesktop.org/~agd5f/linux.git
git fetch --no-tags radeon-alex amd-staging-drm-next-vangogh
git checkout 356e0c5b8e5c7cd698641f3f7605d25ad793b159
# save the attached .config to linux build tree
make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:357:3: error: implicit declaration of function 'ABM_MASK_SH_LIST_DCN301'; did you mean 'ABM_MASK_SH_LIST_DCN20'? [-Werror=implicit-function-declaration]
357 | ABM_MASK_SH_LIST_DCN301(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~~~~
| ABM_MASK_SH_LIST_DCN20
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:357:27: error: '__SHIFT' undeclared here (not in a function); did you mean 'PMD_SHIFT'?
357 | ABM_MASK_SH_LIST_DCN301(__SHIFT)
| ^~~~~~~
| PMD_SHIFT
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:361:27: error: '_MASK' undeclared here (not in a function); did you mean 'PER_MASK'?
361 | ABM_MASK_SH_LIST_DCN301(_MASK)
| ^~~~~
| PER_MASK
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:68:
drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:372:52: warning: initialized field overwritten [-Woverride-init]
372 | #define DCN_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:241:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2'
241 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:243:19: note: in expansion of macro 'BASE_INNER'
243 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:250:14: note: in expansion of macro 'BASE'
250 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:104:2: note: in expansion of macro 'SRI'
104 | SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:442:2: note: in expansion of macro 'SE_DCN3_REG_LIST'
442 | SE_DCN3_REG_LIST(id)\
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:446:2: note: in expansion of macro 'stream_enc_regs'
446 | stream_enc_regs(0),
| ^~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:372:52: note: (near initialization for 'stream_enc_regs[0].DP_SEC_METADATA_TRANSMISSION')
372 | #define DCN_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:241:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2'
241 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:243:19: note: in expansion of macro 'BASE_INNER'
243 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:250:14: note: in expansion of macro 'BASE'
250 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:104:2: note: in expansion of macro 'SRI'
104 | SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:442:2: note: in expansion of macro 'SE_DCN3_REG_LIST'
442 | SE_DCN3_REG_LIST(id)\
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:446:2: note: in expansion of macro 'stream_enc_regs'
446 | stream_enc_regs(0),
| ^~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:372:52: warning: initialized field overwritten [-Woverride-init]
372 | #define DCN_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:241:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2'
241 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:243:19: note: in expansion of macro 'BASE_INNER'
243 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:250:14: note: in expansion of macro 'BASE'
250 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:105:2: note: in expansion of macro 'SRI'
105 | SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:442:2: note: in expansion of macro 'SE_DCN3_REG_LIST'
442 | SE_DCN3_REG_LIST(id)\
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:446:2: note: in expansion of macro 'stream_enc_regs'
446 | stream_enc_regs(0),
| ^~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:372:52: note: (near initialization for 'stream_enc_regs[0].HDMI_METADATA_PACKET_CONTROL')
372 | #define DCN_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:241:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2'
241 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:243:19: note: in expansion of macro 'BASE_INNER'
243 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:250:14: note: in expansion of macro 'BASE'
250 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:105:2: note: in expansion of macro 'SRI'
105 | SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:442:2: note: in expansion of macro 'SE_DCN3_REG_LIST'
442 | SE_DCN3_REG_LIST(id)\
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:446:2: note: in expansion of macro 'stream_enc_regs'
446 | stream_enc_regs(0),
| ^~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:372:52: warning: initialized field overwritten [-Woverride-init]
372 | #define DCN_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:241:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2'
241 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:243:19: note: in expansion of macro 'BASE_INNER'
243 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:250:14: note: in expansion of macro 'BASE'
250 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
vim +357 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c
5dba4991fd338d Bhawanpreet Lakha 2020-05-21 355
5dba4991fd338d Bhawanpreet Lakha 2020-05-21 356 static const struct dce_abm_shift abm_shift = {
5dba4991fd338d Bhawanpreet Lakha 2020-05-21 @357 ABM_MASK_SH_LIST_DCN301(__SHIFT)
5dba4991fd338d Bhawanpreet Lakha 2020-05-21 358 };
5dba4991fd338d Bhawanpreet Lakha 2020-05-21 359
5dba4991fd338d Bhawanpreet Lakha 2020-05-21 360 static const struct dce_abm_mask abm_mask = {
5dba4991fd338d Bhawanpreet Lakha 2020-05-21 @361 ABM_MASK_SH_LIST_DCN301(_MASK)
5dba4991fd338d Bhawanpreet Lakha 2020-05-21 362 };
5dba4991fd338d Bhawanpreet Lakha 2020-05-21 363
5dba4991fd338d Bhawanpreet Lakha 2020-05-21 364
5dba4991fd338d Bhawanpreet Lakha 2020-05-21 365
:::::: The code at line 357 was first introduced by commit
:::::: 5dba4991fd338dc4b2664c0c6b3d80edead4e22c drm/amd/display: Add DCN3 Resource
:::::: TO: Bhawanpreet Lakha <Bhawanpreet.Lakha@xxxxxxx>
:::::: CC: Alex Deucher <alexander.deucher@xxxxxxx>
---
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