Add our HDMI driver owner Algea to list.
On 9/22/20 2:18 AM, Vicente Bergas wrote:
Under certain conditions vop_crtc_mode_fixup rounds the clock
148500000 to 148501000 which leads to the following error:
dwhdmi-rockchip ff940000.hdmi: PHY configuration failed (clock 148501000)
The issue was found on RK3399 booting with u-boot. U-boot configures the
display at 2560x1440 and then linux comes up with a black screen.
A workaround was to un-plug and re-plug the HDMI display.
Signed-off-by: Vicente Bergas <vicencb@xxxxxxxxx>
Tested-by: Vicente Bergas <vicencb@xxxxxxxxx>
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 45 ---------------------
1 file changed, 45 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index c80f7d9fd13f..fe80da652994 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1142,50 +1142,6 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
spin_unlock_irqrestore(&vop->irq_lock, flags);
}
-static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- struct vop *vop = to_vop(crtc);
- unsigned long rate;
-
- /*
- * Clock craziness.
- *
- * Key points:
- *
- * - DRM works in in kHz.
- * - Clock framework works in Hz.
- * - Rockchip's clock driver picks the clock rate that is the
- * same _OR LOWER_ than the one requested.
- *
- * Action plan:
- *
- * 1. When DRM gives us a mode, we should add 999 Hz to it. That way
- * if the clock we need is 60000001 Hz (~60 MHz) and DRM tells us to
- * make 60000 kHz then the clock framework will actually give us
- * the right clock.
- *
- * NOTE: if the PLL (maybe through a divider) could actually make
- * a clock rate 999 Hz higher instead of the one we want then this
- * could be a problem. Unfortunately there's not much we can do
- * since it's baked into DRM to use kHz. It shouldn't matter in
- * practice since Rockchip PLLs are controlled by tables and
- * even if there is a divider in the middle I wouldn't expect PLL
- * rates in the table that are just a few kHz different.
- *
- * 2. Get the clock framework to round the rate for us to tell us
- * what it will actually make.
- *
- * 3. Store the rounded up rate so that we don't need to worry about
- * this in the actual clk_set_rate().
- */
- rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000 + 999);
- adjusted_mode->clock = DIV_ROUND_UP(rate, 1000);
-
- return true;
-}
-
static bool vop_dsp_lut_is_enabled(struct vop *vop)
{
return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en);
@@ -1512,7 +1468,6 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
}
static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
- .mode_fixup = vop_crtc_mode_fixup,
.atomic_check = vop_crtc_atomic_check,
.atomic_begin = vop_crtc_atomic_begin,
.atomic_flush = vop_crtc_atomic_flush,
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