On 2020-09-21 18:57, Will Deacon wrote:
On Wed, Sep 16, 2020 at 12:51:05AM +0100, Robin Murphy wrote:
Midgard GPUs have ACE-Lite master interfaces which allows systems to
integrate them in an I/O-coherent manner. It seems that from the GPU's
viewpoint, the rest of the system is its outer shareable domain, and so
even when snoop signals are wired up, they are only emitted for outer
shareable accesses. As such, setting the TTBR_SHARE_OUTER bit does
indeed get coherent pagetable walks working nicely for the coherent
T620 in the Arm Juno SoC.
I can't help but think some of this commentary deserves to be in the code
as well.
Sure, if you want.
Do you know if this sort of thing is done for other SoCs too, or is this
just a Juno quirk?
Yup, this is a "Midgard working as designed" thing. Juno is the coherent
example I have to hand, but off the top of my head I believe some of the
Exynos SoCs can also use their GPUs coherently if a switch is flipped in
the interconnect to change routing between the CCI and a direct-to-RAM
path; I expect there are probably further Midgard examples that I'm not
aware of. Then there are definitely coherent Bifrost GPUs like the
Amlogic S922/A311 that prompted me to revive this patch, which we
currently drive in "Legacy" mode and thus behave the same way as Midgard
(Bifrost's "AArch64" mode realigns Ish and Osh with the rest of the
system, and instead invents a new "Internal Shareable" value in between
Nsh and Ish to represent the shareability between cores within the GPU
for which Midgard hijacked Ish).
Robin.
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