We're unconditionally using modifiers internally for GFX9+ now.
Signed-off-by: Bas Nieuwenhuizen <bas@xxxxxxxxxxxxxxxxxxx>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 74 ++-----------------
1 file changed, 7 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 25b1c7c821d2..f4a4ca84485a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3793,57 +3793,6 @@ validate_dcc(struct amdgpu_device *adev,
return 0;
}
-static void
-fill_dcc_params_from_flags(const struct amdgpu_framebuffer *afb,
- struct dc_plane_dcc_param *dcc,
- struct dc_plane_address *address,
- const uint64_t flags, bool force_disable_dcc)
-{
- uint64_t dcc_address;
- uint64_t plane_address = afb->address + afb->base.offsets[0];
- uint32_t offset = AMDGPU_TILING_GET(flags, DCC_OFFSET_256B);
- uint32_t i64b = AMDGPU_TILING_GET(flags, DCC_INDEPENDENT_64B) != 0;
-
- if (!offset || force_disable_dcc)
- return;
-
- dcc->enable = 1;
- dcc->meta_pitch = AMDGPU_TILING_GET(flags, DCC_PITCH_MAX) + 1;
- dcc->independent_64b_blks = i64b;
-
- dcc_address = plane_address + (uint64_t)offset * 256;
- address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
- address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
-}
-
-
-static int
-fill_gfx9_plane_attributes_from_flags(struct amdgpu_device *adev,
- const struct amdgpu_framebuffer *afb,
- const enum surface_pixel_format format,
- const enum dc_rotation_angle rotation,
- const struct plane_size *plane_size,
- union dc_tiling_info *tiling_info,
- struct dc_plane_dcc_param *dcc,
- struct dc_plane_address *address,
- uint64_t tiling_flags,
- bool force_disable_dcc)
-{
- int ret;
-
- fill_gfx9_tiling_info_from_device(adev, tiling_info);
-
- tiling_info->gfx9.swizzle =
- AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
-
- fill_dcc_params_from_flags(afb, dcc, address, tiling_flags, force_disable_dcc);
- ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size);
- if (ret)
- return ret;
-
- return 0;
-}
-
static bool
modifier_has_dcc(uint64_t modifier)
{
@@ -4410,22 +4359,13 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
}
if (adev->family >= AMDGPU_FAMILY_AI) {
- if (afb->base.flags & DRM_MODE_FB_MODIFIERS) {
- ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,
- rotation, plane_size,
- tiling_info, dcc,
- address,
- force_disable_dcc);
- if (ret)
- return ret;
- } else {
- ret = fill_gfx9_plane_attributes_from_flags(adev, afb, format, rotation,
- plane_size, tiling_info, dcc,
- address, tiling_flags,
- force_disable_dcc);
- if (ret)
- return ret;
- }
+ ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,
+ rotation, plane_size,
+ tiling_info, dcc,
+ address,
+ force_disable_dcc);
+ if (ret)
+ return ret;
} else {
fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags);
}
--
2.28.0
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