Hi Maxime, Am 01.09.20 um 11:58 schrieb Maxime Ripard: > Hi Stefan > > On Tue, Aug 25, 2020 at 11:30:58PM +0200, Stefan Wahren wrote: >> Am 25.08.20 um 17:06 schrieb Maxime Ripard: >>> Hi Stefan, >>> >>> On Wed, Jul 29, 2020 at 05:50:31PM +0200, Stefan Wahren wrote: >>>> Am 29.07.20 um 16:42 schrieb Maxime Ripard: >>>>> Hi, >>>>> >>>>> On Wed, Jul 29, 2020 at 03:09:21PM +0100, Dave Stevenson wrote: >>>>>> On Wed, 8 Jul 2020 at 18:43, Maxime Ripard <maxime@xxxxxxxxxx> wrote: >>>>>>> In order to avoid pixels getting stuck in the (unflushable) FIFO between >>>>>>> the HVS and the PV, we need to add some delay after disabling the PV output >>>>>>> and before disabling the HDMI controller. 20ms seems to be good enough so >>>>>>> let's use that. >>>>>>> >>>>>>> Signed-off-by: Maxime Ripard <maxime@xxxxxxxxxx> >>>>>>> --- >>>>>>> drivers/gpu/drm/vc4/vc4_crtc.c | 2 ++ >>>>>>> 1 file changed, 2 insertions(+) >>>>>>> >>>>>>> diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c >>>>>>> index d0b326e1df0a..7b178d67187f 100644 >>>>>>> --- a/drivers/gpu/drm/vc4/vc4_crtc.c >>>>>>> +++ b/drivers/gpu/drm/vc4/vc4_crtc.c >>>>>>> @@ -403,6 +403,8 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, >>>>>>> ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); >>>>>>> WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); >>>>>>> >>>>>>> + mdelay(20); >>>>>> mdelay for 20ms seems a touch unfriendly as it's a busy wait. Can we >>>>>> not msleep instead? >>>>> Since the timing was fairly critical, sleeping didn't seem like a good >>>>> solution since there's definitely some chance you overshoot and end up >>>>> with a higher time than the one you targeted. >>>> usleep_range(min, max) isn't a solution? >>> My understanding of usleep_range was that you can still overshoot, even >>> though it's backed by an HR timer so the resolution is not a jiffy. Are >>> we certain that we're going to be in that range? >> you are right there is no guarantee about the upper wake up time. >> >> And it's not worth the effort to poll the FIFO state until its empty >> (using 20 ms as timeout)? > I know this isn't really a great argument there, but getting this to > work has been quite painful, and the timing is very sensitive. If we > fail to wait for enough time, there's going to be a pixel shift that we > can't get rid of unless we reboot, which is pretty bad (and would fail > any CI test that checks for the output integrity). > > I know busy-looping for 20ms isn't ideal, but it's not really in a > hot-path (it's only done when changing a mode), with the sync time of > the display likely to be much more than that, and if it can avoid having > to look into it ever again or avoid random failures, I'd say it's worth > it. i don't want to delay this series. Could you please add a small comment to the delay to clarify the timing is very sensitive? Thanks > > Maxime _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
