Hi Maxime On Wed, 8 Jul 2020 at 18:43, Maxime Ripard <maxime@xxxxxxxxxx> wrote: > > In order to avoid a stale pixel getting stuck on mode change or a disable > / enable cycle, we need to make sure to flush the PV FIFO on disable. > > Signed-off-by: Maxime Ripard <maxime@xxxxxxxxxx> Reviewed-by: Dave Stevenson <dave.stevenson@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/vc4/vc4_crtc.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c > index 7b178d67187f..13fe0e370fb3 100644 > --- a/drivers/gpu/drm/vc4/vc4_crtc.c > +++ b/drivers/gpu/drm/vc4/vc4_crtc.c > @@ -408,8 +408,7 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, > if (vc4_encoder->post_crtc_disable) > vc4_encoder->post_crtc_disable(encoder); > > - CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN); > - > + vc4_crtc_pixelvalve_reset(crtc); > vc4_hvs_atomic_disable(crtc, old_state); > > if (vc4_encoder->post_crtc_powerdown) > -- > git-series 0.9.1 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
